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/Job opportunities/Modeling and optimization of advanced CMOS technology at cryogenic temperatures for quantum computing

Modeling and optimization of advanced CMOS technology at cryogenic temperatures for quantum computing

PhD - Leuven | More than two weeks ago

Physics based transistor modeling to enable large-scale quantum computing
Over the past decades, the continued drive for increasing computing power has fueled the growth and evolution of the mainstream CMOS technology. Physical device scaling, which stood at the basis of this growth, is eventually approaching its limits, as fundamental physical barriers are expected to be reached soon.

For cloud computing applications, additional performance could be gained by operating the servers at liquid nitrogen temperatures at the expense of additional cooling power requirements. Another approach to break scaling limits is quantum computing, which emerges rapidly as a research field that has the potential to bring to practice technologies exploiting massive parallelism, being able to push the computational power way beyond the contemporary realm.

Because of fundamental limits to the tolerable temperature of qubits, one major hurdle towards large-scale integration is their interface to the classical control circuitry to operate them. A promising approach to overcome this problem is to integrate traditional CMOS circuitry to the low-temperature domain for efficient operation of future quantum computers and to reduce limitations due to wiring.

When designing CMOS circuits at such low temperatures, transistor models in modern design kits often fail to capture important physical mechanisms such as the effects of band-tail states, incomplete ionization, tunneling, strain, and other phenomena getting more prominent at those temperatures.

The candidate therefore should develop an accurate physical model for the electrical parameters of CMOS devices from room temperature to liquid Helium temperatures and below. Close interaction with circuit design groups will help to continuously optimize ASICs specifically targeted to operate qubits. Furthermore, the candidate should adjust the necessary design trade-offs and identify opportunities for technology optimization targeted analog and digital circuits at cryogenic temperatures.


Required background: semiconductor physics, transistor-level electrical measurements, programming experience (preferably Python), compact modeling, TCAD experience is a bonus

Type of work: 40% characterization of CMOS devices at various temperatures, 40% data analysis and modeling, 20% literature

Supervisor: Piet Wambacq

Co-supervisor: Bertrand Parvais

Daily advisor: Alexander Grill

The reference code for this position is 2021-052. Mention this reference code on your application form.

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