PhD - Leuven | More than two weeks ago
With Si CMOS technology scaling to sub-5 nm nodes, many challenges appear to maintain power and performance gains of digital circuits at small pitches. As a result, various innovations will be introduced: transistor process optimization (stressors, low-k spacers, and a new channel materials,...), alternative transistor architectures (Nano-Sheet FET, Fork-Sheet FET, Complementary-FET,...), introduction of technology boosters (SuperVia, buried power rails,...). While these elements are primarily developed for logic applications, they will be used in the analog parts of SoCs (PLL, I/O, voltage references, thermal sensors, etc.). However, requirements other than the ‘power-performance-area-cost’ are desired for optimal analog circuit design. For instance, supply voltage reduction is desirable in the digital context, but this can lead to degradation of the signal-to-noise ratio in the analog domain.
The purpose of this PhD is to establish the challenges and opportunities that advanced and future CMOS technologies will bring to analog circuits, and from this, provide innovative solutions.
You will extend the logic device models to include analog specific elements (gate resistance, matching, noise,...). Based on these models, you will explore the benefits/drawbacks of the devices and technology boosters envisioned to continue the scaling roadmap (fork-sheet FET, complementary FET, 2D materials...)
You will design test structures and perform the electrical characterization of the advanced devices processed in imec to evaluate the analog figures-of-merit. You will link technology to analog and mixed-signals circuits design.
Required background: Master in electrical engineering, semiconductor physics, electrical measurements, analog circuit design, programming experience, compact modeling, TCAD experience is a bonus
Type of work: 30% electrical characterization, 50% modeling, 20% literature
Supervisor: Piet Wambacq
Co-supervisor: Bertrand Parvais
Daily advisor: Bertrand Parvais
The reference code for this position is 2021-042. Mention this reference code on your application form.