/Multi-scale Modeling of Reliability Concerns in Ge and SiGe Transistors: from first principles to TCAD

Multi-scale Modeling of Reliability Concerns in Ge and SiGe Transistors: from first principles to TCAD

PhD - Leuven | More than two weeks ago

Defects in the Ge/GeO2 system – beautiful and deadly

The breath-taking development of modern nanoelectronic devices together with the arrival of the mobile era and the Internet of Things raised new challenges and requirements to the next generation transistor structures. One of the major demands is long battery lifetime and tackling this task requires improvement of the channel control, a steeper sub-threshold slope, and hence an improved ratio between ON and OFF currents. 


Fulfilling these requirements relies on the introduction of new device structures, such as fin, nanowire, nanosheet, and forksheet field-effect-transistors (fin, NW, NS, and FS FETs, respectively) as well as novel channel materials. Among the elemental semiconductors, Ge has the highest hole mobility and can be grown epitaxially, resulting in strained Si1−xGex layers. This makes Ge/SiGe the most attractive material for p-channel FETs. However, introduction of any new device can be hindered by reliability concerns. Thus, the ability to fully understand, correctly model, and accurately predict how reliable future devices will behave is as crucial as the ability to fabricate them.


The main goal of this PhD project is to develop a comprehensive physics-based model which can accurately reproduce degradation characteristics of fin, NW, NS, and FS FETs on Ge/SiGe. In these devices, the most detrimental degradation concerns are bias temperature instability (BTI) and hot-carrier degradation (HCD). Both phenomena originate from a collective response of defects activated by an external driving force (such as applied bias, increased temperature, etc.). The situation is further complicated by the confined channels of these novel transistor architectures, giving rise to another detrimental effect, so-called self-heating (SH). Since defect generation is a temperature activated process, SH can substantially accelerate BTI and HCD and therefore these three degradation phenomena should be modeled within an entire framework. Special attention will also be paid to recovery/healing of BTI and HCD at elevated temperatures. Understanding and modeling of these mechanisms should help us elaborate strategies to accelerate device/circuit recovery.    


The basis of this modeling framework will be the set of underlying microscopic defect physics. This information will be obtained with density functional theory calculations. Reliability effects will be considered as various responses of defects triggered by different driving forces. This will be addressed by employing transport simulations and modeling of the degraded devices using traditional TCAD tools. Our model should be able to reproduce and predict changes of transistor characteristics and will be validated over a broad spectrum of devices and stress conditions.


We expect that the applicant has in-depth knowledge in the field of solid-state /semiconductor/semiconductor device physics, solid programming skills (C/C++ and/or Python), eagerness to obtain exciting results and learn. Within this multiscale cross-disciplinary project, the PhD student will be part of a large imec team working in collaboration with academic research centers as well as with industrial partners and therefore good team player skills are desired.

Required background: MS degree in physics, electrical engineering, or materials science

Type of work: 70% modeling, 20% experimental, 10% literature

Supervisor: Michel Houssa

Daily advisor: Stanislav Tyaginov

The reference code for this position is 2024-032. Mention this reference code on your application form.

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