NAND Flash memories modelling and design

Invented 35 years ago and little known to the general public, NAND flash today is a ubiquitous and foundational technology for both mobile computing and datacenters.  In 2020, it was the second largest IC product segment globally and most transistors manufactured today belongs to a NAND Flash Memory.  Since the introduction of the 3D-NAND architecture in 2015, the number of stacked layers has kept increasing [1]. Micron has recently announced up to 232 layers [2]. In parallel, multi-level cells (up to 4 bits per cells) are available to further reduce the bit read margin window. These two elements combined together make the read/write operations of the 3D-NAND ever more challenging. Simultaneously, structural changes are introduced to the 3D-NAND periphery, such as hybrid bonding (Xtacking from YMTC for example [3]). 

The goal of this internship is to develop a basic set of compact models for the NAND device string and its periphery. These elements should enable to simulate the read operation of the NAND memory block. Ultimately, this framework will improve our understanding of how the performance of the NAND memory will evolve in the future.