/Next generation of magnetic memories: from physics modelling to circuit design

Next generation of magnetic memories: from physics modelling to circuit design

PhD - Leuven | More than two weeks ago

Models and design-technology co-optimization for cutting edge magnetic memory devices

Memory is one of the key components in electronic systems where it serves multiple needs – from data storage to caching, buffering, and, more recently, in-memory computing. For many decades, the memory landscape has been unchanged, with a clear hierarchy from caching to storage: fast, volatile SRAMs close to the CPU, DRAM chips for the working memory, non-volatile NAND Flash memory chips for storage.  Despite large improvements in memory density, all these memories are struggling to keep pace with the ever-increasing performance of logic chips and with the tremendous data growth rate This has driven the exploration of alternative memory technologies for standalone as well as for embedded applications. 

One of these emerging memories are magneto-resistive random access memories (MRAMs). MRAM utilizes a magnetic tunnel junction (MTJ) in which a thin dielectric layer is sandwiched between a magnetic fixed layer and a magnetic free layer.  Writing of the memory cell is performed by switching the magnetization of the free layer (the storage layer) Over the years, new ways of writing and reading the magnetization state have been proposed, leading first to Spin-Transfer-Torque Magnetic RAM (STT-MRAM), which is already on the market for eFlash applications, and more recently Voltage-Controlled Magnetic Anisotropy (VCMA) and Spin-Orbit Torque (SOT).


To achieve the next generation of caches to storage class memory solutions, the aggressive scaling on the more traditional STT-MRAM devices might not meet all the reliability, power, and area requirements of future applications. The solutions based on novel switching mechanisms in VCMA and SOT are still under development and need yet to be fully understood. Imec develops these devices integrated in CMOS technologies with leading edge 300mm/EUV tool sets.


This PhD research will fill the gap between the experimental data gathered from in-house grown devices and the circuit cell requirements. You will join a team working on design-technology co-optimization, studying cutting edge magnetic memory devices and coming up with novel model and simulation solutions. You will develop micro-magnetic models capable of incorporating advanced effects like stochastic thermal fields, VCMA influence on SOT devices, magnetic textures on the materials, or the interfacial DMI effects produced by ferromagnet (FM)/heavy-metal (HM) interfaces on SOT switching. You will explore the materials magnetization evolution under these exotic conditions and abstract the key behaviours connecting to the circuit memory elements, testing your models on bitcells and arrays simulations. You will interact directly with the researchers fabricating and characterizing these new devices as well as with the circuit and architecture designers. You will receive the necessary guidance to ramp up quickly in these advanced topics.


Profile : You like physics and mathematical modelling. You are comfortable in programming. Background in digital logic and circuit simulations is a plus.

Required background: Engineering, Physics, or equivalent

Type of work: 60% modeling, 40% circuit simulations

Supervisor: Kristiaan Temst

Co-supervisor: Jan Van Houdt

Daily advisor: Fernando Garcia Redondo

The reference code for this position is 2023-011. Mention this reference code on your application form.

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