Novel chiplet-based architectures for event-based processing nodes at the edge

Chiplets technology is a promising concept to reduce design cost and time of advanced designs while maintaining scalability and flexibility. Moreover, the integration of sensor and compute chiplets within on die can alleviate the throughput bottleneck by using the die-to-die interconnect. Moreover, chiplet technology allows the combination of different technology, each optimized for the intended functionality, and can improve the yield compared to a traditional design implementing all the functionality in one SoC.

This project targets to develop chiplet-based designs for an event-based sensor node at the extreme edge. This includes a system-level exploration of different partitioning and interconnect schemes of such designs and the identification and benchmarking of suitable chiplet modules requiring co-optimization of the hardware and the targeted algorithms.