PhD - Leuven | More than two weeks ago
Chiplets technology is a promising concept to reduce design cost and time of advanced designs while maintaining scalability and flexibility. Moreover, the integration of sensor and compute chiplets within on die can alleviate the throughput bottleneck by using the die-to-die interconnect. Moreover, chiplet technology allows the combination of different technology, each optimized for the intended functionality, and can improve the yield compared to a traditional design implementing all the functionality in one SoC.
This project targets to develop chiplet-based designs for an event-based sensor node at the extreme edge. This includes a system-level exploration of different partitioning and interconnect schemes of such designs and the identification and benchmarking of suitable chiplet modules requiring co-optimization of the hardware and the targeted algorithms.
Required background: Electrical engineering with digital design experience
Type of work: 60% hardware implementation, 25% algorithm implementation, 15% benchmarking
Supervisor: Marian Verhelst
Daily advisor: Matthias Hartmann
The reference code for this position is 2023-099. Mention this reference code on your application form.