PhD - Leuven | More than two weeks ago
A promising approach to overcome this problem is to deploy traditional CMOS circuitry in cryogenic environments for efficient operation of future quantum computers by reducing limitations due to wiring and signal integrity.
Common models used in technology computer aided design (TCAD) often fail to capture important physical mechanisms relevant for cryogenic temperatures such as band-tail states at the silicon-oxide interface, carrier-phonon interactions, or the effects of mechanical strain. As the noise and devices performance of the CMOS circuitry directly affect the fidelity of the qubit control, understanding their limitations is an important goal. You will therefore focus on simulating and understanding the behaviour of CMOS circuitry and the underlying silicon and gate stack at (deeply) cryogenic temperatures.
What you will do:
Who you are:
Required background: material science, microelectronics, computational physics, electrical engineering or related fields
Type of work: 60% simulation of CMOS devices at various cryogenic temperatures 40% literature research
Supervisor: Bart Soree
Daily advisor: Philippe Matagne
The reference code for this position is 2023-041. Mention this reference code on your application form.