Optimization of a ring oscillator model and BEOL sensitivity

Downscaling from one technology node to the next one becomes more challenging. This ever-increasing complexity is not only related to the downsizing of transistors, but also backend of line (BEOL) which serves as nanoscale interconnect.

BEOL scaling is required to fulfill two goals: 1) providing enough resources to connect the FEOL elements and 2) keep pace with power and performance requirements.

To meet the first target, switching to tighter metal pitches and narrower metal lines is necessary. However, it increases both resistance and capacitance of BEOL and therefore increases the power consumption and degrades the performance.

To overcome these problems new methods and scaling boosters are required to optimize both R and C of BEOL. Implementing such boosters comes with extra costs and complexities. Hence, as the first step, an in-depth understanding of the correlations between BEOL parameters and block performance is required. This understanding is then applied to simulate the impact of boosters on the performance of the circuit.

Electronic design automation (EDA) tools can simulate the impact of the BEOL scaling boosters and give us a reliable estimation of the performance in block level. However, achieving place and route (PnR) data is time consuming and resource demanding. To speed up this phase we would like to mimic the behavior of any IC by means of a simple circuit.

For this purpose, we have chosen ring-oscillator (RO) as the canary to represent more complex circuits.

The aim of this project is to build a model in spice, which allows us to study the sensitivity of our RO model to the BEOL related parameters which impact the performance of the circuit.

Requirements to fulfil this project:

• Understanding of CMOS technology
• Strong programming skills in MATLAB and/ or Python, C++, Perl
• Basic knowledge in spice simulations
• Knowledge of Linux
• Communicative and active team player