Oxide semiconductor for select transistor of memory devices

Leuven - PhD
|
More than two weeks ago

Contribute to the development of new transistors that will enable 3-dimensional memory structures

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Amorphous metal oxide semiconductor like Indium-Gallium-Zinc-Oxide (IGZO) is the most commonly used oxide material in liquid crystal displays (LCDs) and organic light-emitting diode (OLED) displays manufacturing due to their field-effect mobility >10 cm2/V·s, good uniformity over large glass substrates sizes, low temperature process and relatively good bias-thermal stress stability. Besides driving innovative thin-film transistors for display applications, IGZO is also seen as a premium material to help the semiconductor industry to further improve system scaling like placing the transistors in the Back-End-Of-Line of a chip rather than in the periphery.

Last but not least, because of their extremely low leakage current and relatively good carrier mobility, oxide semiconductor IGZO can make nonvolatile memories more power efficient while maintaining the data writing and reading at very high speed. In addition, integration of such material in DRAM cell architecture opens up the possibility of 3D DRAM integration, which helps to continue the DRAM scaling roadmap. Especially the low-leakage property has triggered companies and research institutes to investigate the potential for new memory devices. Indeed, while having a very low junction leakage, the transistor can be connected to a storage node without significant charge leakage from that node. However, these cells exhibit quite low on-currents and therefore, new schemes and improved material processing have to be explored in order for these devices to become practical.

The PhD aims at defining the required material specifications in order to enable these new memory device architectures and also at inventing new cell structures that are more compatible with the particular properties of these materials. This implies: understanding the material properties, fitting them on particular cell structures, processing and evaluating these structures and arrive at a model for circuit implementation.


Required background: Master in electrical engineering or Master in nanoscience and nanotechnology

Type of work: 20% literature, 30% technology study, 40% experimental work, 10% modeling

Supervisor: Paul Heremans, Jan Van Houdt

Daily advisor: Ludovic Goux

The reference code for this position is 1812-17. Mention this reference code on your application form.

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