/Packaging solutions for 3D integration of superconducting qubits

Packaging solutions for 3D integration of superconducting qubits

PhD - Leuven | More than two weeks ago

Explore imec's 3D integration expertise to develop scalable architectures for large-scale superconducting quantum processors

Quantum computing aims to solve some of the most difficult problems human-kind faces more efficiently than classical computing algorithms are capable of. As a result, there is growing interest in industry and leading academic-research labs to push the current limits of this new paradigm of computing in order achieve quantum advantage [1]. Qubits, which are the fundamental computational unit of a quantum computer can be physically implemented using various platforms, namely, photons, electron and nuclear spins, quantum dots, ions, neutral atoms, superconducting anharmonic oscillators (superconducting qubits) etc. Out of these, superconducting qubits have emerged as one of the prime candidates for large-scale implementation of quantum processors. These qubits, along with their control and readout circuitry, can be fabricated using standard cleanroom processing technology using superconducting materials and their properties can be fully engineered by design, giving the experimenter a great deal of flexibility [2].

  

Qubits, however, are prone to their environmental and thermal noise. Superconducting qubits, in particular are also sensitive to losses in various material interfaces which causes energy relaxation and dephasing. This leads to infidelity in their state preparation and readout. To protect qubits from decoherence and errors thereof, several error correction protocols can be implemented [3], where, a single logical qubit can be encoded in many physical qubits below a finite error threshold. The overhead required in terms of physical qubits for error correction can reach several thousands to about a million qubits. Lateral, planar 2D wiring schemes seen in present day superconducting quantum processors cannot be used in next generation processors where large number of qubits are required.

 

3D wiring technology used in standard CMOS processing offers a natural solution to this problem. Here, the qubit chip(s) and the readout and control chip(s) can be stacked together and interconnections between them can be made using though silicon vias (TSVs) and flip-chip bonding [4]. The challenges, however, are (1) in choosing the right materials and processes which are compatible with qubit fabrication, (2) design and simulation of the necessary qubits and their control and readout elements, (3) understanding losses in these structures, (3) room temperature and cryogenic characterization of devices, (4) designing experiments to study reliability under various conditions, (5) developing intelligent packaging solutions, to name a few. At imec, we are focused on addressing these many challenges by leveraging our in-house expertise in quantum computing and 3D integration. Our state-of-the-art 200mm and 300mm cleanrooms provide an ideal environment for the production of high-quality, low-variability devices [5].

 

To advance our efforts in 3D integration of superconducting qubits and solve some of the challenges highlighted above, we invite highly-motivated and interested students to pursue a PhD in this direction. We seek someone with a strong background in electrical (preferably microwave) characterization, materials characterization, simulation (HFSS, Comsol, ADS) and programming (preferably python). Experience in microwave engineering and quantum mechanics is a strong plus.

 

References:

 

[1] F. Arute et al., Quantum Supremacy Using a Programmable Superconducting Processor, Nature 574, 7779 (2019).

[2] P. Krantz, M. Kjaergaard, F. Yan, T. P. Orlando, S. Gustavsson, and W. D. Oliver, A Quantum Engineer’s Guide to Superconducting Qubits, Applied Physics Reviews 6, 021318 (2019).

[3] A. G. Fowler, M. Mariantoni, J. M. Martinis, and A. N. Cleland, Surface Codes: Towards Practical Large-Scale Quantum Computation, Phys. Rev. A 86, 032324 (2012).

[4] D. R. W. Yost et al., Solid-State Qubits Integrated with Superconducting through-Silicon Vias, Npj Quantum Inf 6, 59 (2020).

[5] J. Verjauw et al., Path toward Manufacturable Superconducting Qubits with Relaxation Times Exceeding 0.1 Ms, Npj Quantum Inf 8, 1 (2022).



Required background: Electronics engineering, Material science

Type of work: 25% Design/Simulation, 65% experimental, 10% Literature

Supervisor: Kristiaan Degreve

Daily advisor: Vadiraj Ananthapadmanabha Rao, Jaber Derakhshandeh

The reference code for this position is 2023-037. Mention this reference code on your application form.

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