Pathfinding methodology for future logic technologies

Downscaling from one technology node to the next one becomes ever more challenging. This increase in complexity is not only related to the downsizing of transistors, but also the interconnect (backend of line) becomes a severe bottleneck for scaling. New interconnect technology like graphene, new interconnect concepts like active interconnect or even new devices such as 2D channel-FETs need fast learning cycles to provide proper technology directions and specifications.

In order to build fast learning cycles that allow providing directions and specifications to the technology research team, we need to develop a methodology that can capture the fundamental features of the technology such as BEOL RC statistics and device drive and capacitance. Usually Ring Oscillators are the first canaries used for technology benchmarking but in advanced technologies they fail in providing accurate guidelines. This comes from the fact that SoC power and performance are driven by a wide variety of contexts and functions inside the SoC, which also vary between different SoC applications (high perf CPU, low power CPU, GPU, AI accelerator,...). However, performing full place-and-route (PnR) loops involving complex digital library designs is tedious and does not allow wide technology excursions necessary in an early pathfinding process. To enable realistic predictions of future technology and how they may affect digital block-level performance, fast optimization loops are required. To achieve this PnR data from past implementations are used to generate statistical models that are extrapolated to predict the impact of technology on designs. These statistical models can be used in simple circuit benchmark like ring oscillators and digital logic paths to enrich their correlation to design and provide more accurate predictions of future technologies.

The aim of the PhD work is to build up an automated model based on PnR data as input and comprehensive statistical models as output. The model can the be used to assess the power-performance response to disruptive technology evolutions such as BEOL boosters (new materials, new dielectrics,...), new interconnect concepts such as active interconnect and backside interconnect and even new devices such as 2D or CNT devices. This model can then be used to provide the necessary directions for technology