/Pathfinding a monolithic fabrication of 3D Nanofabric Programmable Coprocessors

Pathfinding a monolithic fabrication of 3D Nanofabric Programmable Coprocessors

PhD - Leuven | More than two weeks ago

Building Logic in 3D requires a fabrication process that is co-developed with 3D Logic computations in nanofabrics

Now that the CMOS roadmap is showing strong signs of saturation in terms of PPAC (power, performance, area and cost) figures of merit, 3D SRAM and logic integration is becoming a very attractive option. Exploiting the third dimension can result in high density ICs without requiring costly feature size reduction while also decreasing the interconnect length, which improves power and performance. However, direct stacking of multiple CMOS FEOL-BEOL layers in a sequential way does nothing for cost/transistor reduction and this presents a strong barrier to mainstream adoption. 3D NAND Flash memories have overcome this hurdle by a pure monolithic scaling process with a mask and process step scheme that is shared across all layers. However, to extend this towards SRAM and logic we see several technical and scientific challenges. Solving the coexistence of SRAM cells and logic elements in the same plane enables a new storage/computing paradigm: computation at the memory. Datapaths transforming the data flows to/from the memory locations, accelerate custom boolean functions and DSP flows, saving massive energy from the avoided data movement and speeding up workload computations. However the design of such datapaths is limited by the logic layout, imposing metal, active, and gate material lines layouts not to cross in the same plane.

To perform true logic computations in 3D the entire CMOS process needs to be re-visited. Inspired by the 3D NAND-flash process and the 3D DRAM process one needs to extend the flow to enable rich enough compute capability which will most likely require more complex connectivity within the 3D structure. This may also force the logic to operate in a non-CMOS fashion. Several options have already been proposed but few have been confronted with the manufacturing complexity in 3D.

 

The goal of this PhD is to build a concept process flow for nanofabric computing that matches the expectations set by the computing experts. This work will be conducted hand-in-hand in a true DTCO process with the circuit design team to trade process feasibility with logic functionality. This work will explore the process constrains for various logic concepts. This will start from an established 3D memory flow, explore its extension to 3D SRAM as a starting point while the compute team will provide various logic extensions that should then be confronted to their process feasibility



Required background: Motivated, creative and eager to learn with Master’s degree in physics or electronics engineering

Type of work: 20% literature, 60% modelling, 20% experimental

Supervisor: Paul Heremans

Co-supervisor: Serge Biesemans

Daily advisor: Hans Mertens

The reference code for this position is 2023-026. Mention this reference code on your application form.

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