/Patterning Defectivity Investigation for High-NA EUV Lithography

Patterning Defectivity Investigation for High-NA EUV Lithography

Research & development - Leuven | More than two weeks ago

You will work together with a team of lithography specialists within an international environment in a modern 300 mm semiconductor cleanroom using advanced tools at the leading-edge technology.

Patterning Defectivity Investigation for High-NA EUV Lithography

 

Electronics offer innovative ways to communication, work and live and integrated circuits (ICs) appear in various applications in our daily lives. Over the past five decades, the ICs have seen a continuous increase of computing power while at the same time increasing performance. To achieve this, the number of transistors on the ICs must increase per unit area. This trend, known as Moore’s law, predicts that the number of transistors on an IC doubles every two years. In lithography, the smallest feature size, or critical dimension (CD), possible depends on the wavelength 𝜆 of the source, the numerical aperture (NA) of the optical system and a correction factor 𝑘1 that accounts for non-ideal behavior. The miniaturization of feature sizes has been achieved mainly by shortening the wavelength of exposure tools. Currently, extreme ultraviolet light (EUV), with a wavelength of 13.5 nm, is the new generation lithography that enables more powerful chips. The further development of EUV lithography (EUVL) is heavily based on implementing the so-called high-NA EUVL, in which the current NA-value of 0.33 is increased to 0.55 to get even better resolution. In anticipation of the high-NA technology, the focus is now shifted towards resist development.

 

The resist has an important part to play in every lithography process by transferring the information present on the mask (e.g. all the patterns) to the substrate when irradiated with light. Throughout the optimization of lithographic technologies, a first challenge is the continuous downscaling of the film thickness of the lithography materials (resist and underlayers). The reason for this is twofold in that going to smaller wavelengths (i.e. higher energy electrons) means that the absorption of the radiation can only be kept homogeneous by reducing the film thickness. Therefore, because of the continuous downscaling envisioned for high-NA technology, both photoresist film thicknesses (10 – 35 nm) and underlying film thicknesses (3 – 20 nm) are approaching the ultra-thin film regime. The scaling down in features and related aspect ratio has significant implications on the pattern quality at photoresist level (after development) and at pattern transfer level (after etching), thus the defectivity of the patterning is currently one of the biggest priorities in EUVL.

 

This project will explore the limitations of resist patterning with respect to process and material characteristics that happen with pushing the patterning resolution or going to the ultra-thin film regime necessary for high-NA. This work will significantly contribute to the understanding of resist performance and inherent limits. It will lead to help the design of new photoresists for EUV lithography. The student will work in the international research facility of imec interacting with multiple advanced 300mm equipment for patterning defectivity investigation and analysis and material partners. To accomplish this task, the student must have a chemistry and/or physics, nanotechnology or materials science background, basic knowledge on statistics and a liking for the design of experiments, their execution, and data analysis.


 

A stochastic nano-defect on a line-space pattern. Top-Down image by scanning electron microscope (SEM)



Type of project: Combination of internship and thesis

Duration: 9 months

Required degree: Master of Engineering Science, Master of Engineering Technology, Master of Science

Required background: Chemistry/Chemical Engineering, Materials Engineering, Mechanical Engineering, Nanoscience & Nanotechnology, Physics

Supervising scientist(s): For further information or for application, please contact: Danilo De Simone (Danilo.DeSimone@imec.be) and Christophe Beral (Christophe.Beral@imec.be)

Imec allowance will be provided.