Performance and power analysis of emerging memory

Magnetic random access memory (MRAM) has made extensive progresses to be a working cache memory solution with nonvolatility, high speed and low power consumption. Moreover, to predict the system level impact using MRAM based cache, a modelling tool is required, which uses various attributes such as access time, cycle time, power consumption (leakage/dynamic), and area. For SRAM, such tool is available like CACTI from HP labs, which uses above mentioned attributes and facilitate the system level impact. This work will focus on developing a memory macro modeling framework like CACTI which uses analytical equations, calibrated to state-of-the-art device and interconnect models from scaled technologies developed at IMEC.  

In this work the candidate will interact with different imec groups working on technology development, and design to identify the challenges with large MRAM based cache. In the large size cache, interconnects play a critical role in determining the overall delay and consume more than 50% of the energy. The primary objective of this work is to develop a CACTI like framework for MRAM based cache that will be used to estimate system level impact.