Performance and variability modelling of ultra-thin body silicon and 2D material FETs.

2D materials are explored as candidates for channel materials in highly scaled transistors thanks to their excellent electrostatic control and pristine van der Waals surfaces. Ab initio modelling of transition-metal dichalcogenides (TMDs) shows promising performance.^[1] However, due to their van der Waals nature, 2D materials face significant integration challenges, including increased variability.^[2] Alternatively, through standard CMOS scaling, ultra-thin body (UTB) silicon approaches a quasi-2D material and may offer similar electrostatic control. While their integration path is more straightforward, the lack of a pristine van der Waals interface may induce even higher process variability. Two main questions thus arise: (1) can UTB silicon be as performant as native 2D materials, and (2) how does the variability of UTB silicon compare to 2D materials?

To address these questions, a physics-based compact model is indispensable. At imec, significant effort is devoted to developing compact models that capture the behavior of FinFETs, nanosheets, and ideal 2D transistors, as predicted by advanced TCAD and quantum transport simulators. However, the physics of UTB and 2D devices is fundamentally different than that of bulk materials. In low-dimensional materials, the material’s interface is inseparable from the material itself. Interactions with the surroundings are much stronger, and materials parameters are a strong function of their environment. Effects such as electron-phonon scattering, remote-phonon scattering, surface roughness, trapped charges, and oxide dangling bonds must be correctly captured in the compact model to describe the performance and variability of these inherently non-ideal devices.

As a Ph.D. candidate, you will need to distil the complex material and device physics that governs the non-ideal quasi-2D device into approximate analytical methods to be implemented in a performant compact model. You will collaborate closely with the advanced simulation groups at imec to fit and adapt your model to the latest device predictions. To reliably capture the process variability, you will incorporate the latest experimental data from imec’s state-of-the-art cleanroom. At the interface of device and circuit design, you will work with device experts at imec to compare the power, performance, cost and area (PPAC) of these quasi-2D devices. Finally, you will collaborate with circuit designers at imec and KU Leuven to understand the relevant parameter space and manage the variability challenges of these highly scaled devices. Through this work, you will help build the CMOS scaling roadmap into the future.