On the physical limits of transistor operation to enable low-power electronics for quantum computing applications

Quantum computing emerges rapidly as a research field with the potential to bring to practice technologies exploiting massive parallelism and to push computational power way beyond the contemporary realm for a certain class of problems. Because of fundamental limits to the tolerable operating temperature of some of the leading candidate-qubits, one major hurdle towards large-scale integration is their interface to the classical control circuitry required to operate them.

A promising approach to overcome this problem is to deploy traditional CMOS circuitry in cryogenic environments for efficient operation of future quantum computers by reducing limitations due to wiring and signal integrity. One of the major hurdles for large-scale deployment of circuits at 4K or mK temperatures is their power consumption, motivating efforts in reducing the circuit operating voltage by leveraging the back-gate of fully depleted silicon-on-insulator (FDSOI) devices.

Applying large voltages to the back-gate however raises concerns on the stability and the parameter drift of devices and circuits due to charge trapping in the buried oxide. On top of that, device-to-device variations may turn out as a limiting factor in the race for the reduction of noise as well as static and dynamic power consumption of circuits. Understanding the impact of time-zero and time-dependent variability due to charge trapping at the front- and back-oxides of FDSOI devices and circuits is therefore of great importance to help optimizing cryogenic circuits.

What you will do:

• You will measure the electrical impact of defect generation and charge trapping in FDSOI devices from room-temperature down to cryogenic temperatures, with a special focus on the impact of back-gate biasing.
• You will investigate the time-zero and time-dependent variability of devices and selected demonstrator circuits at deep cryogenic temperatures.
• Your studies will help to minimize power consumption of cryogenic CMOS circuits by exploring the limits of supply voltage reduction at cryogenic temperatures.

Who you are:

• You have a master’s degree in electrical engineering, microelectronics, physics, or related fields.
• You would like to understand the impact of charge trapping and variability of FDSOI technology on the design of low-power circuits at cryogenic temperatures.
• You want to gain hands-on measurement experience in our cryo-lab.
• You like to take the initiative; you are persuasive and assured, while keeping a constructive attitude within the team.
• Given the international character of imec, a fluent knowledge of English is necessary.

Figure 1: Static and dynamic power consumption of a cryo-CMOS multiplexer in 28nm bulk technology operated at mK temperatures. The goal of this PhD will be to show pathways to minimize power consumption by exploring the limits of supply voltage scaling on FDSOI transistors.