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/Job opportunities/Physical modeling of transistor degradation effects for reliable circuit design beyond the 7 nm node

Physical modeling of transistor degradation effects for reliable circuit design beyond the 7 nm node

PhD - Leuven | More than two weeks ago

Enable additional performance and reliability gains of cutting-edge VLSI technologies

In order to improve transistor performance from one generation to another, new materials and new device architectures are being continuously introduced (e.g., nano-sheet transistors).  But with these innovations, new challenges appear for ensuring their reliability, i.e., limited degradation during operation. As transistors are downscaled toward atomic dimensions, each stochastically behaving defect has potentially a substantial impact on the device operation.   

Up to now, reliability has been guaranteed at the technology level.  Such approach is too restrictive, as it does not take into account the function of each transistor in the circuit.  Some transistors are used less than others, while careful and controlled boosting of biases of other transistors beyond their nominal reliability limit could enormously benefit the performance of the entire application.  A reliability-aware circuit design, accounting for individual device degradation, is therefore being considered.

Thorough, physics-based models are already being developed and improved for the various degradation mechanisms (such as Bias Temperature Instability, Hot Carrier Degradation, etc.) occurring in different regions of the FET {Vgate, Vdrain} operating space.  These mechanisms include charging of preexisting defects in the gate dielectrics and simultaneous generation of new defects, e.g. by hot carriers, compounded by significant channel temperature increases due to FET “self-heating”. However, to understand the impact of the degradation on circuits, the existing physical insights need to be converted to compact models usable in SPICE-level simulations. 

The Thesis work therefore encompasses: i) converting the already-developed physical models into such reliability-aware compact models capable of describing the degradation of all major FET parameters, in the entire operating space as a function of an arbitrary stress history, ii) enabling the simulation of FET degradation in various analog and digital circuits and understanding the implications for various circuit parameters, and iii) design, layout, and measurement of test circuits to validate the developed compact models and the simulation methodology.

 

Required background: semiconductor device physics, transistor-level circuit simulations, transistor-level circuit design, layout, and electrical measurements

 

Type of work: 40% compact model development, 30% modeling and simulations, 30% design and validation

Supervisor: Georges Gielen

Daily advisor: Ben Kaczer, Bertrand Parvais

The reference code for this position is 2021-039. Mention this reference code on your application form.

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