PhD - Leuven | More than two weeks ago
Solve the mysteries of charge carriers, phonons, and defects
Microelectronics, based on Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), pervades all aspects of our lives and enables progress in virtually all fields of humankind. Although transistor scaling has been actively exploited for more than 50 years (“Moore’s Law”), the MOSFET technology has still to go for many years. However, any further developments and progress rests on two pillars: (i) employment of confined transistor structures such as FinFETs, nanowire (NW) FETs, forksheet FETs, and (ii) introduction of novel materials, including channel materials such as monocrystalline SiGe, polycrystalline Silicon (poly-Si), and amorphous Indium-Gallium-Zinc Oxide (IGZO), which have their application in display, memory, and logic applications. However, introducing any new transistor node can be prevented by reliability concerns, which should be thoroughly understood and accurately modeled.
In confined transistor structures, the channel is surrounded by dielectric layers with a low thermal conductivity and this peculiarity give rise to a new (compared to the “traditional” planar FET) reliability issue called “self-heating” (SH) which accelerates other degradation mechanisms such as hot-carrier degradation (HCD) and bias temperature instability (BTI). Under real stress/operating conditions, HCD and BTI are driven by non-equilibrium (hot) carriers and while modeling these detrimental phenomena, one needs to solve the Boltzmann transport equation for carriers. A thorough description of SH should be based on modeling of phonon transport. The situation is made even more complicated for disordered semiconductors, such as poly-Si and IGZO, where carrier transport is dominated by hopping and granularity should be taken into account.
The general goal of this PhD work is therefore to develop a modeling framework covering the atomistic level of defect description, carrier/phonon transport, and modeling of the degraded devices. The information of microscopic defect properties will be provided with first principles calculations by density functional theory (DFT) conducted by the DFT group of imec. The extracted defect properties will be incorporated into the device simulator and the reliability simulator to model trapping and detrapping rates (constituting BTI) as well as bond rupture reactions leading to creation of charge traps (the main mechanism of HCD). This activity will be pursued in parallel with extension of the open source carrier Boltzmann transport equation solver by incorporation of new disordered materials and corresponding scattering and conduction mechanisms. This will be coupled to the Boltzmann transport equation solver for phonons to enable accurate modeling of SH and its impact on trapping and defect generation reactions. This multiscale modeling approach will thoroughly capture the intricate physical picture behind reliability issues in ordered and disordered semiconductor systems and ensure comprehensive and predictive reliability modeling.
We expect that the applicant has in-depth knowledge in the field of solid-state /semiconductor/semiconductor device physics, good programming skills (C/C++ and/or Python), eagerness to obtain exciting results and learn. Within this multiscale cross-disciplinary project, the PhD student will be part of a large imec team working in collaboration with academic research centers as well as with industrial partners and therefore good team player skills are desired.
Required background: MS degree in physics, electrical engineering, or materials science
Type of work: 70% modeling, 20% experimental, 10% literature
Supervisor: Michel Houssa
Daily advisor: Stanislav Tyaginov
The reference code for this position is 2022-126. Mention this reference code on your application form.