/Physics of fault attacks on emerging active memories for IOT

Physics of fault attacks on emerging active memories for IOT

PhD - Leuven | More than two weeks ago

Develop in depth understanding of a mechanism behind fault attacks induced state change in MRAM and FeRAM memory arrays for an application in cryptography.

In the internet-of-things (IOT) era billions of devices are getting connected to the internet or a local server. The generated data is stored locally to the devices rather than on a remote secure server-room/clouds. There are significant efforts underway to make these IOT devices more energy efficient by utilizing emerging non-volatile memories. All these devices contain secret data and keys, which is required to store or transmit the data. As the devices are usually cheap and easy to access, adversaries can mount a variety of physical attacks on them to break their security. Therefore, understanding the (physical) implications of attack mechanisms and schemes on these devices is essential. 

Voltage gate assisted spin orbit torque magnetic random-access memory (VGSOT-MRAM) is one of these emerging non-volatile memories, that has a potential for use in embedded cache, microcontroller units (MCU), and embedded flash applications. On the other hand, also ferroelectric random-access memory (Fe-RAM) has a potential to replace the existing dynamic random-access memories.

Side channel, micro-architectural and fault attacks are a major challenge in cached and embedded flash security. A famous example is the Rowhammer attack on DRAMs1. In row hammering attacks repeated access to the rows results in flipping of bits in adjacent rows, which allows untrusted code to escape its sandbox. As the density of memory cells increases, and new types of memories appear, also new types of Rowhammering attacks are becoming a persistent threat to chip security.

In this Ph.D., the aim is to study the memory cells and array switching behavior beyond normal operating conditions. The student will perform in-depth fault attacks and investigate whether state changes can be induced on MRAM and FeRAM cell and arrays. The student will try to model the experimental results to understand the fault induced switching mechanisms. Eventually, the student can investigate row hammering and clock/voltage fault attacks on memory arrays controlled by FPGA boards. From the physcial analysis the student can deduce the countermeasures to improve the memory security.



1 Google Online Security Blog: Introducing Half-Double: New hammering technique for DRAM Rowhammer bug (googleblog.com)




Required background: M.Sc. Physics, M.Tech. Electronics/Electrical Engineering, M.Tech. Computer Science, M.Tech. Cyber Security.


Type of work: 20% literature study, 40% experimental work, 40% Simulation/modelling.

Supervisor: Ingrid Verbauwhede

Daily advisor: Ankit Kumar, Robin Degraeve

The reference code for this position is 2023-010. Mention this reference code on your application form.

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