Pioneering ARM DSU big.LITTLE Cluster Optimization

Imec's STCO program is designed to pioneer future technology scaling, overcoming challenges such as the scaling wall, memory wall, power wall, and cost wall. We aim to engineer high-density, cost-effective Integrated Circuits (ICs), optimizing Power, Performance, Area, Cost, and Temperature (PPACT). By fostering innovation and adopting a system-level perspective, we confront these challenges head-on.

We are seeking a motivated intern with a keen interest in system-level design and optimization. The successful candidate will participate in the design and implementation of an Arm DSU big.LITTLE cluster, employing Arm HP as the big and Arm HD as the LITTLE. Responsibilities include defining realistic workloads and benchmarks for the cluster, developing and optimizing compiler configurations for efficient workload mapping onto the big and LITTLE cores. Our current toolchain supports single Processing Element (PE), big or LITTLE, simulation, and we aspire to handle more complex workloads on both big and LITTLE cores.

The intern will also engage in dynamic tasks like workload partitioning, with possible consideration of aspects like TinyML inference thermal-aware mapping. Further responsibilities include addressing the challenges associated with CPU migration and multi-core task scheduling. Leveraging the DSU's support for energy-aware scheduling software on both big and LITTLE cores, the intern will analyze simulation results, identify bottlenecks, and propose optimizations to boost system performance, power, and thermal efficiency.

We believe that adopting an innovative, system-level perspective is crucial to engineering high-density, cost-effective ICs optimized for PPACT. This internship offers a unique opportunity to be at the cutting edge of technological advancement, addressing scaling and power challenges.

Required background: We are seeking candidates with a background in Electronics/Computer Engineering, possessing a robust understanding of Computer Architecture and Embedded Systems. Proficiency in C, Python, Cross-compilation, SystemVerilog/VHDL, RTL simulation, and Post-synthesis analysis is necessary. Experience with ARM IP development will be considered a plus.

Master's degree: Master of Engineering Science; Master of Science; Master of Engineering Technology 

Master program: Computer Science; Electrotechnics/Electrical Engineering 

Type of work: This role enriches your learning experience, providing a blend of theoretical knowledge and practical application. The work is divided into 25% literature study to enhance theoretical comprehension and 75% hands-on digital design.

Type of Project: Combination of internship and thesis 

Duration: 6 - 9 Months 

Promotor: Francky Catthoor

For more information or application, please contact the daily advisors Yukai Chen (yukai.chen@imec.be) and Dwaipayan Biswas (dwaipayan.biswas@imec.be)
 

Imec allowance will be provided for students studying at a non-Belgian university.