Plasmonics Logic

Leuven - PhD
|
More than two weeks ago

Tailoring & modulating surface plasmons for computation

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CMOS technology through transistor scaling has been the main driver for the huge productivity growth registered over the past 50 years. However, transistor scaling is approaching its physical limits and new devices, circuits and architectures are being investigated to continue the performance scaling.

To replace the silicon transistor, many devices have been proposed and are currently at varying levels of maturity – from concept to experimental demonstration. Conceptually they range from transistors with a different channel material (III-V semiconductors, graphene or other 2D materials) to devices where energy filtering can be employed (tunnel FET) to devices which are based on spin or to excitons or surface plasmons.

Surface plasmons are collective oscillations of an electron gas at the interface between a metallic and dielectric material. They are currently being considered as a means of carrying and processing information in computer chips since surface plasmons can be extremely confined spatially and support high frequencies (into the 100 THz range). Also, surface plasmons are interesting for possible applications in logic devices based on interference. Simple devices and logic gates based on plasmon interference have already been demonstrated experimentally. 

In spite of the fast advances in plasmonics, there are still important missing blocks before logic plasmonic circuits become feasible.  The system level tradeoffs in such a logic system have to explored in more detail. This includes the combination of compact, coherent plasmon excitation, ultrafast and compact phase modulation, waveguiding and electrical detection. 

The main target in this PhD is to conceptually and experimentally study plasmonic circuits through electromagnetic simulations, their interaction with detectors and optical waveguides and to implement compact and fast modulation schemes. This work will benefit from extensive in-house know-how on CMOS, plasmonics and optical interconnects. The experimental work will be carried out in a lab to fab fashion, using where possible fab processes and components and lab processing where needed. Special attention will be given to device characterization and modeling.​

 

 

Required background: Physics, Electrical engineering

 

Type of work: 40% modeling/simulation 40% experimental 20% literature

Supervisor: Pol Van Dorpe, Iuliana Radu

Daily advisor: Iuliana Radu

The reference code for this position is 1812-47. Mention this reference code on your application form.

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