Gent | More than two weeks ago
CMOS technology through transistor scaling has been the main driver for the huge productivity growth registered over the past 50 years. However, transistor scaling is approaching its physical limits and new devices, circuits and architectures are being investigated to continue the performance scaling, including architectures that step away from using electronic signals, moving into the optical or photonic domain.
To replace the silicon transistor, many devices have been proposed and are currently at varying levels of maturity – from concept to experimental demonstration. Conceptually they range from transistors with a different channel material (III-V semiconductors, graphene or other 2D materials) to devices where energy filtering can be employed (tunnel FET) to devices which are based on spin or to excitons or surface plasmons.
Surface plasmons are collective oscillations of an electron gas at the interface between a metallic and dielectric material, resulting in an very confined optical wave packet. They are currently being considered as a means of carrying and processing information in computer chips since surface plasmons can scale down to much smaller dimensions that traditional dielectric optical waveguides (e.g. silicon photonics) and support the same high frequencies (into the 200-500 THz range). Also, surface plasmons could also be interesting for possible applications in logic devices based on interference. Simple devices and logic gates based on plasmon interference have already been demonstrated experimentally.
In spite of the fast advances in plasmonics, there are still important missing blocks before logic plasmonic circuits become feasible. Especially the system-level tradeoffs in such a logic system have to be explored in more detail. This includes the combination of compact, coherent plasmon excitation, ultrafast and compact phase modulation, waveguiding and electrical detection. It is important, when building a new architecture for digital logic, that the underlying analog behaviour of the building blocks and the system is well understood.
The main target in this internship is to generate a circuit-level and system-level simulation model of the entire plasmonic logic system to gain this deeper understanding and evaluate the potential and limitations of such a plasmonic logic architecture. This includes building simplified models of the different components, with the primary goal to predict system performance and to elucidate system level trade-offs, especially in the presence of imperfections (e.g. parasitic reflections, or variation between building blocks).
The candidate ideally has a background in electrical/photonic engineering or physics and is proficient in the use of Python and/or Matlab.
Type of work: 20% literature, 40% coding, 40% simulation & data interpretation
Type of project: Combination of internship and thesis, Internship
Duration: 6-12 Months
Required degree: Master of Engineering Science, Master of Science
Required background: Physics, Electrotechnics/Electrical Engineering, Other
Supervising scientist(s): For further information or for application, please contact: Wim Bogaerts (Wim.Bogaerts@imec.be) and Pol Van Dorpe (Pol.VanDorpe@imec.be) and Christian Haffner (Christian.Haffner@imec.be) and Francky Catthoor (Francky.Catthoor@imec.be)