CMOS technology through transistor scaling has been the main driver for the huge productivity growth registered over the past 50 years. However, transistor scaling is approaching its physical limits and new devices, circuits and architectures are being investigated to continue the performance scaling.
To replace the silicon transistor, many devices have been proposed and are currently at varying levels of maturity – from concept to experimental demonstration. Conceptually they range from transistors with a different channel material (III-V semiconductors, graphene or other 2D materials) to devices where energy filtering can be employed (tunnel FET) to devices which are based on spin or to excitons or surface plasmons.
Surface plasmons are collective oscillations of an electron gas at the interface between a metallic and dielectric material. They are currently being considered as a means of carrying and processing information in computer chips since surface plasmons can be extremely confined spatially and support high frequencies (into the 100 THz range). Also, surface plasmons are interesting for possible applications in logic devices based on interference. Simple devices and logic gates based on plasmon interference have already been demonstrated experimentally.
In spite of the fast advances in plasmonics, there are still important missing blocks before logic plasmonic circuits become feasible. The system level tradeoffs in such a logic system have to explored in more detail. This includes the combination of compact, coherent plasmon excitation, ultrafast and compact phase modulation, waveguiding and electrical detection.
The main target in this PhD is to experimentally demonstrate plasmonic waveguide circuits, demonstrate the coupling with detectors and photonic waveguides. In addition you will investigate compact and fast modulation schemes. To design and understand the individual components and the circuit, you will perform electromagnetic simulations. This work will benefit from extensive in-house know-how on CMOS, plasmonics and optical interconnects. The experimental work will be carried out in a lab to fab fashion, using where possible fab processes and components and lab processing where needed. Special attention will be given to device characterization and modeling.
Required background: Engineering Technology, Electronics engineering, Physics, Photonics
Type of work: 15% Literature, 45% Experimental, 40% Modeling
Supervisor: Pol Van Dorpe
Daily advisor: Iuliana Radu, Niels Verellen
The reference code for this position is 2020-011. Mention this reference code on your application form.
Chinese nationals who wish to apply for the CSC scholarship, should use the following code when applying for this topic: CSC2020-07.