/Power Delivery Network Exploration for Sequential 3D

Power Delivery Network Exploration for Sequential 3D

Leuven | More than two weeks ago

Power integrity for sequentially integrated heterogeneous system
The impressive growth of the semiconductor industry in the past few decades has been driven by the CMOS technology scaling. Miniaturizing the CMOS devices provides larger integration density, higher performance while lowering the power consumption. However, as CMOS scales down to node N3 and beyond, gate length scaling becomes increasingly difficult if not impossible. Furthermore, the resistance of local interconnect in advanced nodes becomes the main bottleneck in extracting performance benefits from CMOS technology scaling. Achieving power, performance, and area gain from CMOS technology scaling as predicted by Moore’s law thus requires innovation in technology, device architecture, circuit, and system design. 3D integration has been perceived as the promising candidate for extending Moore’s law without scaling the critical device/interconnect dimensions.

In this work, the candidate will interact with different imec groups working to identify the challenges with power delivery network design for a sequential 3D partitioned system. The primary objectives are to come up with sequential 3D system floor planed power delivery network schemes to improve power integrity.

Type of project: Combination of internship and thesis, Thesis

Required degree: Master of Engineering Science

Required background: Electrotechnics/Electrical Engineering

Supervising scientist(s): For further information or for application, please contact: Rongmei Chen (Rongmei.Chen@imec.be) and Shairfe Muhammad Salahuddin (Shairfe.Muhammad.Salahuddin@imec.be)

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