PPACT Evaluation of a Vector Functional Unit

Imec's STCO program, with its mission to pioneer future technology scaling, is designed to meet the challenge of scaling wall, memory wall, power wall, and cost wall head-on. We aim to engineer high-density, cost-effective Integrated Circuits (ICs) that optimize Power, Performance, Area, Cost, and Temperature (PPACT). We do this by embracing innovation and viewing these challenges from a system-level perspective.

During this internship, you will have the unique opportunity to shape and explore potential computing architectures suitable for future technologies. Your primary task will be the RTL (Register-Transfer Level) design of a Vector Functional Unit (VFU) for a wide vector processor to boost high-performance SIMD (Single Instruction, Multiple Data) executions. This role also involves implementing data communication channels for the VFU, which includes designing a very wide register, a tile shuffler, and river routers to establish a robust data communication network capable of clustering VFUs. Finally, generate a broadly usable RTL block netlist of VFU and its communication channels.

Further, you will be required to conduct RTL simulations using real workloads, such as deep learning inference, and perform power and thermal analysis at the Gate level. This valuable hands-on experience will allow you to better understand the intricacies of semiconductor technology and its challenges. Throughout this internship, you will work closely with our team of system architects and PPACT researchers. This collaboration will offer the chance to evaluate your implementation in conjunction with future technology trends and research.

Required background: We are seeking candidates with a background in Electronic/Computer Engineering, with a strong understanding of Computer Architecture, Microarchitecture/ISA. Proficiency in C, Python, SystemVerilog/VHDL, and RTL simulation is necessary.

Master program: Electrotechnics/Electrical Engineering; Computer Science 

Master's degree: Master of Engineering Technology; Master of Science; Master of Engineering Science 

Type of work: This role is designed to enrich your learning while providing hands-on experience. As such, the work is divided into 25% literature study to enhance your theoretical knowledge and 75% hands-on RTL development and physical design to immerse you in practical, innovative solutions.

Type of Project: Combination of internship and thesis 

Duration: 6 - 9 Months 

Promotor: Francky Catthoor

For more information or application, please contact the daily advisors Yukai Chen (yukai.chen@imec.be) and Dwaipayan Biswas (dwaipayan.biswas@imec.be)

Imec allowance will be provided for students studying at a non-Belgian university.