/Principal Design Implementation Lead

Principal Design Implementation Lead

Research & development - Leuven | More than two weeks ago

Enable next generation AI hardware through HW-SW Codesign for HPC

Principal Design Implementation Lead

What you will do

The Compute System Architecture (CSA) unit at imec desires to build zetta-scale AI/HPC hardware and software solutions co-designed. We are backed by a broad in-house R&D expertise, creating a new AI computing paradigm that will move the industry forward for many years to come. Designed in tune with advanced silicon geometry, novel communication technology, our architecture provides high-performance AI computing solutions in reliability, security, and power consumption at scale. We analyze emerging usage models, build hardware and software prototypes for data-driven computing hardware capable of zetta-scale performance.
The CSA team is looking for a Principal Design Implementation Lead within the hardware team. With you, we are going to launch the microprocessor with high computing power and energy efficiency that will enable imec to assert its leadership and technological independence in strategic applications for next generation applications such as AI model training, HPC, drug discovery and metaverse processing.
You are motivated by an experience within an industrial research startup unit with fast growth and high visibility, having access to top notch silicon technology (beyond 7nm), a team of technical experts from multiple domains interested in true hw-sw codesign, all in a very competitive international environment.
Your main objectives/responsibilities will be:
  • Lead microarchitecture development and specification of hardware IP prototyping- From early high-level architectural exploration, through micro-architectural research and arriving at a detailed specification.
  • RTL ownership: Development, assessment and refinement of RTL design to target power, performance, area and timing goals.
  • Validation: Support testbench development and simulation for functional and performance verification.
  • Performance exploration and correlation: Explore high performance strategies and validate that the RTL design meets targeted performance.
  • Implement RTL and synthesize design within constraints of area, timing, performance and power.
  • Participate in design reviews, test plan and verification coverage definition.
  • Analyze SoTA intellectual property and participate in activities related to protecting intellectual property.
  • Collaborate and create networks with different functional teams.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will define the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. In everything we do, your future colleagues are guided by the imec values of passion, excellence, connectedness and integrity. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth. 

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits.
This is your opportunity to define and help drive imec’s system architecture roadmap to build the AI technology of the near and far away future.

Who you are

  • BS/MS or PhD degree in Electrical Engineering or Electronics Engineering.
  • 10+ years of SoC micro-architecture and design experience.
  • Extensive experience in designing and integrating communication centric IPs within complex SoCs.
  • Strong understanding of hardware design, timing analysis, clock domain crossing, lint and verification.
  • Experience in IP, Algorithm Model development using C/C++/SystemC.
  • A Technical Lead with a collaborative way of working. You enjoy sharing experience and knowledge with colleagues and transparency and integrity are important in your professional relationships.
  • Hands on lab bring-up and debug experience and familiarity with lab instruments.
  • Your networking skills, creativity, persistence, and passion for what you do are highly valued. 
  • We are looking for your excellent communication skills in English, as you will work in a multicultural team and closely with our partners.
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