Principal Engineer, RISC-V SoC Architecture (Multiple Positions)

What you will do

The Compute System Architecture (CSA) unit at imec desires to build RISC-V based zetta-scale AI/HPC hardware and software solutions co-designed. We are backed by a broad in-house R&D expertise, creating a new AI computing paradigm that will move the industry forward for many years to come. Designed in tune with advanced silicon geometry, novel communication technology, our architecture provides high-performance AI computing solutions in reliability, security, and power consumption at scale. We analyze emerging usage models, build hardware and software prototypes for data-driven computing hardware capable of zetta-scale performance.

Memory and Interconnect Subsystems play a critical role in the design of next generation AI/HPC system architectures. As an Principal Engineer, RISC-V SoC Architecture, you will be part of our platform modelling team and contribute to the scope of either or both of those subsystems. Your role spans a combination of the following responsibilities: (1) Driving the specification, development, and integration of component models of relevant components of the memory / interconnect system in our platform modelling infrastructure (performance models with awareness of power/area implications); (2) Model validation and calibration against known hardware; (3) As a part of the co-design exercise — across hardware, software (or workload models), technology options — interacting with other stakeholders to participate in performance analysis and subsequent model iterations to improve system level impact (PPA).

You have a relevant background in building models, hands-on, for real systems,  and you are motivated by an experience within an industrial research startup unit with fast growth and high visibility, with access to top notch silicon (beyond 7nm), a team of technical experts from multiple domains interested in true HW-SW co-design, all in a very competitive international environment. 

Your responsibilities include:

• SOC and IP Architecture for compute, accelerator and network technologies.
• Perform feasibility analysis, put together architectural specifications, put together floorplans, SOC integration and analyze high-level performance and power characteristics
• Ability to thrive in a pathfinding environment with less-defined design guidelines
• Lead technical communication and collaboration with customers and ensure a high level of customer satisfaction
• Manage and drive cross-site, cross-function team collaborations
• Be able to provide technical guidance to engineers
• Be able to travel domestic or internationally when required

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. Candidates with current working rights in the UK are also welcome to work from our imec office in Cambridge, UK, and candidates with working rights in the US can work remotely from any location within the US. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth. 

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits. 

Who you are

• Master’s or Doctoral degree in Computer Science or Electrical/Computer Engineering 
• 8+ years experience working with either of the memory or interconnect subsystem verticals in an industrial context:e.g., SoC interconnect / interconnects for large multicore / D2D / chiplet interconnect / memory and cache controllers / data movement protocols, etc.,
• Experience in high-leveland detailed hardwaremodel development(SystemC / Gem5 /  SST /Other) andPPA analysis
• Experience in working with RISC-V based HPC systems
• Strong background in modern C++ along with other relevant programming skills (e.g., python, scripting)
• Strong debugging and analytical skills to debug modelling / performance issues.
• Effective communication skills in English, allowing you to perform well in a multicultural team and in close collaboration with our partners. 
• Quickly embrace new technological paradigms. 
• Pragmatic and concise in your approach, you enjoy working with a focus on (collaborative) problem solving