Principal Architect Interconnect IP

What you will do

The Compute System Architecture (CSA) unit at imec desires to build zetta-scale AI/HPC hardware and software solutions co-designed. We are backed by a broad in-house R&D expertise, creating a new AI computing paradigm that will move the industry forward for many years to come. Designed in tune with advanced silicon geometry, novel communication technology, our architecture provides high-performance AI computing solutions in reliability, security, and power consumption at scale. We analyze emerging usage models, build hardware and software prototypes for data-driven computing hardware capable of zetta-scale performance.

Interconnect subsystems (both on/off-chip) continue to play a critical role in the design of next generation AI/HPC system architectures. As a principal architect of interconnect subsystems, you will be part of our platform modelling team wherein you help model, evaluate, and design high-performance interconnect fabrics with associated policies/protocols at various levels of the hierarchy (i.e., on/off-chip) to support workloads in a next generation zetta-scale system for AI/HPC. Your role spans a combination of the following responsibilities: you drive the development and integration of models (mainly performance/cycle-level-detail, but also power and area) of relevant components of the interconnect system (NoCs, chip-to-chip/node-to-node interconnects, topologies, protocols, QoS) in our platform modelling infrastructure; you ensure a sufficiently high level of model maturity by calibrating model performance to relevant equivalent systems; you understand workload patterns and work with relevant teams to evaluate system-level impact of various design choices (PPA and cost) in the interconnect subsystem. 

You are motivated by an experience within an industrial research startup unit with fast growth and high visibility, having access to top notch silicon technology (beyond 7nm), team of technical experts from multiple domains interested in true HW-SW co-design, all in a very competitive international environment. 

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth. 

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits. 

Who you are

• Master’s or Doctoral degree in Computer Science or Electrical/Computer Engineering 
• 7+ years experience working with uncore / communication / interconnect subsystems / interconnects for large multicore/multinode HPC systems
• Extensive experience in designing and integrating communication centric IPs within complex SoCs. 
• Experience in high-level model development / PPA analysis
• Strong background in modern C++ along with other relevant programming skills (e.g., python, scripting) working in a Linux/Unix environment.  
• Strong debugging and analytical skills to debug modelling / performance issues.
• You have effective communication skills in English, allowing you to perform well in a multicultural team and in close collaboration with our partners. 
• You quickly embrace new technological paradigms. 
• Pragmatic and concise in your approach, you enjoy working with a focus on (collaborative) problem solving.