Profiling and Characterization of Next-gen HPC/AI Applications

The Compute System Architecture Unit at imec is researching next-generation large-scale heterogeneous computer architectures for next-generation HPC and AI applications, such as real-time digital twins and accessible personalized medicine. The team is responsible for algorithm research, runtime management innovations, performance modeling, architecture simulation and prototyping for these future applications and the future systems to execute them, to reach multiple orders of magnitude better performance, energy-efficiency, and total-cost-of-ownership.

In order to design such architecture, one important requirement is the better understanding of these workloads. It is important to understand the behavior of these workloads under different architectural assumptions such as, network topologies, memory sizes, pipeline depth/width, SIMD/SIMT, vector processors, custom accelerators, and so on. There are several existing tools and frameworks (that allow building custom tools) to profile the behavior of applications such as Intel Pin for x86, NVBit for GPUs, and Timeloop for accelerators. Moreover, profiling large workloads generate a lot of data and manually analyzing such huge data is infeasible. There is a lot of ongoing research to characterize the profiled data. In this internship, the candidate will work towards deriving useful insights by profiling and characterizing the next-gen workloads. Along with research, this would involve hands-on coding of the profiling tools and custom characterization methods. This activity will happen at imec, Leuven for a period of 6 months approx.