/Realization of Logic-In-Memory Operation on Crossbar Array

Realization of Logic-In-Memory Operation on Crossbar Array

Master projects/internships - Leuven | More than two weeks ago

The thesis is aimed at enabling Logic-in-memory computation using novel Non-Volatile Memory (NVM) technologies.

​The separation between the processing units and memory unit requires data transfer over energy-hungry buses. This data transfer bottleneck is popularly known as the memory wall.

The overhead in terms of energy and delay associated with this transfer of data is considerably higher than the cost of the computation itself. This problem can be alleviated by Logic-in-memory (LiM) computation, which is enabled when the same physical characteristics of the devices can be utilized for both memory and logic operations. Multiple emerging memory technologies hold the promise for logic-in-memory computation.

Specifically, we are interested in memories that permit stateful logic, where the logical states are represented as resistive state of the devices and at the same time, are capable of computing. In this work, the primary goal would be to characterize and understand the suitability of crossbar arrays for performing LiM computation (NOR, NAND or other universal gate families). The candidate would get to work with crossbar arrays based on different emerging Non-Volatile Memory (NVM) technologies. Phase Change RAM (PC-RAM), Ox-RAM and Spin Transfer Torque - Magneto-Resistive RAM (MRAM) are among the more mature NVM technologies that can be used for crossbar array designs. Voltage Controlled Magnetic Anisotropy (VCMA) MRAM is a more recent NVM with interesting characteristics that can also be used for crossbar array designs. However, replacing the heavily optimized existing storage memory design architectures with these NVM based crossbar designs that can help facilitate LiM is easier said than done. These highly dense crossbar 3D architectures need heavy technology optimizations, ultra-low sensing schemes, low leakage and low power architecture solutions to be effective. Each technology also comes with a set of inherent flaws, like write endurance limitation, or high access latency, etc. The plethora of challenges present a vast design exploration space.

In addition, the thesis would look at enabling design automation to map arbitrary Boolean functions using such crossbar arrays, for applications related to security and AI.


  • Mandatory: Digital Electronics
  • Preferred: Memory Design skills and knowledge of Non-Volatile Memory technology
  • Optional: Python



Type of project: Thesis

Duration: 6 months

Required degree: Master of Science, Master of Engineering Technology, Master of Engineering Science

Required background: Computer Science, Electrotechnics/Electrical Engineering, Nanoscience & Nanotechnology

Supervising scientist(s): For further information or for application, please contact: Debjyoti Bhattacharjee (Debjyoti.Bhattacharjee@imec.be), Manu Perumkunnil (Manu.Perumkunnil@imec.be) and Mohit Gupta (mohit.gupta@imec.be).

Imec allowance will be provided for students studying at a non-Belgian university.