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/Job opportunities/The role of hybrid graphene/metal stacks in interconnect applications

The role of hybrid graphene/metal stacks in interconnect applications

PhD - Leuven | More than two weeks ago

The next conductor for revolutionizing microprocessor fabrication
The potential application space for 2D-materials has been increasing over the past few years with various proposals [1] in the field of opto-electronics, sensors, transistors, and interconnects. In this study, the focus is on the interconnect application by evaluating graphene as an alternative for Cu. For more than two decades Cu dual damascene is the standard interconnect material and module used in commercial circuits due to its superior properties and low cost. With further scaling of the technology nodes also here, limitations are encountered which are induced by grain and surface scattering, self-heating and electromigration. Graphene capped metals are being explored as potential alternative. The overall Figure-of-Merit (FOM) to monitor for process and material selection is defined by a combination of 4 key parameters: resistance, capacitance, power consumption and energy delay product (EDP). While extensive research has been conducted for benchmarking [2] graphene performance towards Cu-standard, many questions remain open not only with respect to integration feasibility but also towards fundamental understanding. While a clear advantage is seen for the line-to-line capacitance caused by the reduced wire thickness, a pronounced challenge remains the achievable carrier density in graphene wires which is limited by the low density of states. To enhance carrier density, various doping schemes can be considered such as surface doping, doping via intercalation for multi-layer graphene stacks and substitutional doping. Since most of these processes are difficult to control or can reduce the overall mobility, they are likely not implementable in a 300mm integration flow.
In this study, you will investigate the properties of metal/graphene hybrid structures [3]. A comprehensive study will contain learning from both physical and chemical characterization cross-checked with electrical verification. Moreover, the required test structures are fabricated in the lab with the correct device architectures needed for correct probing. Electrical testing will include standard resistance measurements but also include the determination of temperature coefficient of resistance (TCR), breakdown voltages and the relevant reliability assessments.

[1] Akinwande, D., Huyghebaert, C., Wang, C. et al. Graphene and two-dimensional materials for silicon technology. Nature 573, 507–518 (2019).
[2] Modelling of graphene for interconnect application, Antonino Contino, PhD dissertation, KULeuven, 2019
[3] Achra et al., Characterization of interface interactions between Graphene and Ruthenium for application in hybrid interconnects; IITC 2020

Required background: material physics, electron device physics

Type of work: 80% experimental work, 20% literature and modeling

Supervisor: Ingrid De Wolf

Co-supervisor: Zsolt Tokei

Daily advisor: Inge Asselberghs

The reference code for this position is 2021-009. Mention this reference code on your application form.