Senior Digital Architect for Neuromorphic IC design
What you will do
Our goal is to exploit neuromorphic
and related non Von Neumann architectures to solve real-world problems with
orders of magnitude gains versus conventional solutions. We are working on a
wide range of neuro-inspired architectures that we efficiently implement in
ICs. We are exploring many computational domains such as spiking neural
networks, online and on-chip learning of all forms, probabilistic inference,
function approximation, sparse coding and dynamic control. Our novel
technologies will enable a wide range of smart IoT applications.
We are seeking a distinguished digital architect to take on a leadership role at the forefront of neuromorphic computing. You will play a major role in directing architecture development across both internal team and external collaborations. You will work closely with algorithms and application specialists to define our next generation neuromorphic processors for IoT applications. You will be the technical lead of a team designing and implementing an ultra low power digital event driven IC for neural networks. Your focus will be on its architecture and the efficient implementation of our spiking neural network algorithms that will support a wide range of applications. Starting with system-level modeling methodologies for architectural design and covering definition of sub-blocks, implementation and testing. You will evaluate the trade-offs between power, area, performance and scalability. The final aim is that the designs will be productized by our industrial semiconductor partners. Apart from coaching other digital designers, you will also contribute to the definition of new R&D topics in discussion with experts in other domains.
Your main tasks & responsibilities are:
- Take the technical lead in the definition and implementation of digital hardware in state-of-the-art SoCs and mixed-signal ICs based on event driven algorithms.
- Perform architecture studies for neuromorphic IC’s and memory centric architectures to run new applications.
- Contribute to the definition of new R&D topics in our technical leadership team, write project proposals and lead initial technical planning.
- Interface towards our partners and external project members.
- Develop and refine design concepts and architectures.
- Develop energy efficient hardware implementations to support new algorithms.
- Design and implementation of low-power HW implementation (RTL).
- Deliver results in time in accordance to the project plan.
- Document and present results.
What we do for you
By joining the IoT & Neuromorphic team at the High Tech Campus in Eindhoven, you will be part of a team of disruptive innovators and thinkers. Together, with our Researchers and Engineers, you can work on systems that make our sensors smarter and combine them in smart building applications. We drive the Internet of Things (IoT) by developing innovative solutions for massive, heterogeneous sensor networks to connect billions of devices together. Imec is a reference in the design of ultra-low power electronics, low-power algorithms to increase intelligence and data security, and in all aspects of data science.
Who you are
- Master degree with minimal 7 years of professional experience.
- 7+ years of experience in RTL development (VHDL/(system-)Verilog) with Tape-Out experience.
- 5+ years of experience in ANN and preferable spike based neural networks.
- Proven track record in optimizing neuromorphic architectures and sub-systems that are operating near the limitations of technology, with challenging resource constraints, and preferably in the field of ultra-low power.
- Hands-on experience with FPGA prototyping and measurement equipment (silicon evaluation).
- Knows the fundamentals in digital communications, signal processing, and processor architectures.
- Proven ability to liaise across own discipline, i.e. with analog designers, algorithmic designers, embedded SW and application engineers.
- Experience with System-Level Modeling (e.g., Matlab, Phyton).
- Knowledge of emerging memories (Resistive, Magnetic, Correlated electric etc.) is a plus.
- Knowledge of low power techniques; hands-on experience with the industry standard UPF methodology is a plus.
- Knowledge of PERL and shell scripting is a plus.
- In depth understanding of various established memories (DDR, Flash, SRAM, eDRAM, ROM, EEPROM) is a plus.
- Good understanding of all types of neural networks, mapping to hardware (SoC, crossbar) and implications on TOPS/W, Accuracy, Area and Power is a plus.
- Solid background of VLSI design, hands-on experience with digital design flow, from RTL to GDS2 is a plus but not needed.
- Proven ability to solve problems.
- Quick learner and flexible in doing activities which might not be your core-activity.
- Flexible team player, actively helping other team members and sees changes as an opportunity to learn and grow.
- Proactive attitude, taking responsibility for the process from specification to validation, including communication and alignment with different stakeholders.
- Feels challenged in an R&D environment.
- Good communication skills in English (written and spoken).
InterestedAre you interested in this position and do you want to learn more about it, then you can talk to Frank Wolfs, Talent Acquisition Lead. You can reach Frank via +31(0)6-50837563.
Click on ‘apply’ to submit your application. You will then be redirected to e-recruiting.