Senior Digital Designer for RISC-V HDL Design (Multiple Positions)

What you will do

The Compute System Architecture (CSA) unit at imec desires to build zetta-scale AI/HPC hardware and software solutions co-designed. We are backed by a broad in-house R&D expertise, creating a new AI computing paradigm that will move the industry forward for many years to come. Designed in tune with advanced silicon geometry, novel communication technology, our architecture provides high-performance AI computing solutions in reliability, security, and power consumption at scale. We analyze emerging usage models, build hardware and software prototypes for data-driven computing hardware capable of zetta-scale performance.

The CSA team is looking for a Senior Digital Designer for HDL Design within the hardware team. With you, we are going to enable the IP needed for the efficient execution of workloads in a zetta-scale computing system. You will be responsible for designing and modeling high-performance accelerator, un-core and network-on-chip architectures across the breadth of heterogeneous core complex portfolio. Hierarchical cluster architectures are essential to producing high-performance multicore architectures that can scale to 1000+ cores. You should have strong knowledge of bus protocols, synthesis tools, process nodes, VLSI design, and successful industry experience with deployment of IPs in large SoC projects while working in a collaborative environment.

You are motivated by an experience within an industrial research startup unit with fast growth and high visibility, having access to top notch silicon technology (beyond 7nm), team of technical experts from multiple domains interested in true hw-sw codesign, all in a very competitive international environment.

You will:

• Read and analyze the system requirement and architecture requirement documents.
• Work with architecture team to mature the design specifications for further implementation.
• Code in HDL to implement desired functions based on design specifications.
• Design or integrate the testbench for design verification.
• Generate design report to detail functions and behavior.
• Generate application guide for h/w and s/w integration.
• Work with integration teams to participate in design integration.
• Work with model teams to build model of the design and get it integrated.
• Work with verification teams to verify the design with module-test or system-level-test.
• Work with firmware teams support developing firmware and drivers.
• Package the design into IP for future reuse.
• Guide and review the junior in the team as the mentor.
• Define bus components micro-architecture while considering performance/power/area tradeoff.

What we do for you

We offer you the opportunity to join one of the world’s premier research centers in nanotechnology at its headquarters in Leuven, Belgium. Candidates with current working rights in the UK are also welcome to work from our imec office in Cambridge, UK, and candidates with working rights in the US can work remotely from any location within the US. With your talent, passion and expertise, you’ll become part of a team that makes the impossible possible. Together, we shape the technology that will determine the society of tomorrow.

We are committed to being an inclusive employer and proud of our open, multicultural, and informal working environment with ample possibilities to take initiative and show responsibility. We commit to supporting and guiding you in this process; not only with words but also with tangible actions. Through imec.academy, 'our corporate university', we actively invest in your development to further your technical and personal growth. 

We are aware that your valuable contribution makes imec a top player in its field. Your energy and commitment are therefore appreciated by means of a market appropriate salary with many fringe benefits. 

Who you are

• At least 8 years of digital HDL design
• Experience of designing in Verilog and System Verilog
• Experience of using Synopsys DesignWare and Arm IPs
• Experience of implementing chiptop required reset and clocking logics
• Experience in either Trace & Debug or DFT implementation
• Experience in IP, Algorithm Model development using C/C++/SystemC.
• You are a constructive team player and actively share experience and knowledge with colleagues.
• Your networking skills, creativity, persistence, and passion for what you do are highly valued.
• We are looking for your excellent communication skills in English, as you will work in a multicultural team and closely with our partners.
• You possess the ability to react quickly and adapt to changes.
• Familiarity with CPU/GPU architecture is a big plus.