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/Job opportunities/Sensing mechanical stress in integrated circuits

Sensing mechanical stress in integrated circuits

PhD - Leuven | More than two weeks ago

Development of sensing solutions integrated in the state-of-the-art ICs for in-situ monitoring of induced mechanical stresses

​Performance and reliability of microelectronics components to great extent is determined by the packaging assembly technology and thermo-mechanical interactions between the chip and the package. Following  Moore’s law scaling trends (i.e. smaller and faster), the new generations of integrated circuits are moving away from the mature 20th century technologies towards the alternative device architectures (FinFets, SOI devices, vertical FETs) in the front-end-of-line and alternative materials (low dielectric constant materials, rare metals) in the back-end-of-line. These new materials and architectures are currently being introduced to meet challenging demands in terms of performance and price. Moreover, heterogeneous integration of many Si chips in one integrated circuit using vertical micro- and nano- interconnects paves the way to further extension of performance and, in many cases, even adding extra functionality thus making it possible to create a whole system on the single chip. Such 3-D integration, however, involves new technological challenges such as extreme thinning of silicon chips down to hundreds of nano-meters and making vias in it.

The new technologies both already implemented in the state-of-the-art integrated circuits and the ones which are still to come, being currently in the development phase, make, however, the chips more vulnerable to thermal and mechanical stresses. The safe reliability margins of the heterogeneous integration and packaging technologies are narrowing down and thus it is becoming important to get more understanding about mechanical stress levels induced during the assembly process. During its active life the chip sees different environmental conditions up to very extreme cases as in automotive and space applications. These extreme levels of temperatures, humidity, mechanical shocks can also induce high mechanical stresses in the ICs. It is, thus, becoming very important to monitor mechanical stresses induced in fragile silicon devices both during their manufacturing and assembly but also in-situ during their operational life. This understanding can enable the prediction of possible failures in the integrated circuits and their mitigation.

The principle of mechanical stress sensing is based on the piezoresistive effect in silicon. Thus, a semiconductor device can be used as a stress sensor. Single resistors or transistors (sometimes arranged in pairs) are hence often used to determine stress through a current read-out, despite their weak sensitivity (~500ppm/MPa). However, unlike temperature for which the sensing solutions are integrated in the circuits since many years, mechanical stress is a vector value where every component will have its own effect on the sensing device and can have different effects on the mechanical reliability of the ICs. To achieve a reliable and efficient extraction of these different components, new approaches are required, such as embedded stress extraction circuits. 

The ultimate aim of this PhD work is to create a set of tools (designs, architectures, calibration and data processing methodologies) which can be integrated in the state-of-the-art ICs and used for in-situ monitoring of induced mechanical stresses.

The PhD work will consist of:

  • Analysis of the existing circuit architectures and design solutions to measure mechanical stresses,
  • Conception and development of innovative circuit/device approach for stress sensing using available CAD and simulation tools (Cadence, Calibre, TCAD), followed by prototyping in state-of-the-art semiconductor foundries,
  • Electrical/mechanical characterization of the prototypes, using known calibration techniques (4points bending) as well as developing new ones to evaluate and compare the new sensors with respect to the state of the art,
  • Development of an empirical model based on the theory of piezoresistivity and experimentally obtained piezoresistive calibration coefficients,
  • data analysis and reporting.

The PhD candidate should have strong background in electrical engineering, linear algebra, physics of semiconductors. He will work in close collaboration with circuit designers, thermal, mechanical and semiconductor physics experts at imec.


Required background: Electrical Engineering, Physics of Semiconductors

Type of work: This PhD includes device design and simulations (35%), electrical and mechanical measurements (25%), development of new tools for mechanical calibration (15%), mathematical modelling and data analysis (25%).

Supervisor: Ingrid De Wolf

Daily supervisors: Vladimir Cherman, Gaspard Hiblot

The reference code for this position is 2021-031. Mention this reference code on your application form.