PhD - Leuven | More than two weeks ago
Designing and testing novel and reliable internal and external I/O interfaces in STCO scaling era.
System-technology-co-optimization (STCO) has been proposed as a promising path for further scaling beyond the 5nm technology node [1-3]. More and more (sub-)system functions will be integrated in one chip with special 3D functional die-to-die or 2.5D interposer stacking architectures. I/O interface circuits between different functional dies are one of the major design challenges in these STCO vertical stacking integrations. This I/O related challenge is not only from the inherent parasitics of the vertical architectures, such as through Silicon via (TSV) structures, but also from electrical reliability concerns of electrostatic discharge (ESD) during the stacking process. Even more, traditional ESD protection designs can bring significant parasitic capacitive load which can further deteriorate the functional performance of these vertical I/O interface circuits.
High density, high bandwidth, and low power die-to-die (or named internal) I/O interface circuits are required in the state-of-the-art STCO applications. Future 2.5D or 3D systems will contain thousands of I/Os, and to achieve the high-performance requirements, reducing the power switching noise and the energy-per-bit is essential. Moving to low-swing signaling as removing all the parasitics impedances on the signal path are the solutions to achieve these goals. In particular, ESD protections account for a significant part of the parasitic loads and total area which prevents the scaling down the I/O footprint. Therefore, appropriate ESD mitigation strategies which include both design of integrated ESD protection circuits and ESD prevention in the manufacturing environment, are key factors for designing internal I/O circuits that connect the stacked dies. However, wafer-level ESD testing and ESD assessment of the vertical stacking process are both fundamental to designing the proper internal I/O circuits. We already know that the Charged Device Model (CDM)-like ESD events pose the biggest threat in the vertical stacking process. Even so, CDM ESD testing on wafer-level is a novel and not fully understood process, with instruments as the Low-Impedance Contact CDM (LICCDM) tester still under development. The ESD assessment of the vertical stacking process is an even bigger unknown, with only theoretical results available .
Last but not least, recently, backside (BS) power delivery network (PDN) which is implemented with nano-TSV and buried power rail (BPR) has been considered as a crucial scaling booster towards future advanced technology nodes in STCO era . The process options of this BS PDN can also introduce the full backside interconnections for external I/O interfaces. Thus, the external I/O signals will need to receive from or transmit to the backside of a die (or a wafer) by the nano-TSV and BPR structures which can induce significant impact of parasitic capacitive load on signal paths. More importantly, these external I/O interfaces which have the direct connections to the final assembly bumps will need to meet the general component-level (or even the system-level) ESD specifications. An optimized external I/O interface with a robust ESD protection can become another main challenge in the STCO scaling era.
In this doctoral program, firstly, the high performance internal and external I/O interface designs for 3D/2.5D stacking and BS-PDN technologies will be investigated, respectively. Then, the corresponding ESD protection and prevention strategies will also be fully evaluated to achieve more reliable internal and external I/O interfaces in STCO scaling era.
KU Leuven supervisor: Piet Wambacq (VUB)
Focus of work: Circuit Design; Metrology & characterization
The reference code of this topic is 2021-038. Please mention this on your application.
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