/Substrate effects in advanced RF technologies

Substrate effects in advanced RF technologies

PhD - Leuven | More than two weeks ago

Explore RF substrate technologies

In order to enable the next generation of communication systems (5G, 6G), the circuits are getting more complex than ever and are composed today of several chips, each implemented in different technologies optimized for a specific function. Downscaling of CMOS technology has allowed the integration of high-speed transceivers on Silicon chips, but power amplifiers using III-V technologies, and high-performance switches fabricated on SOI substrates remain the preferred choice for RF Front-End circuits. In order to develop sustainable, cost and power efficient RF systems, the current research at imec for RF front-end module technologies addresses: (i) the integration of high-speed III-V and III-N devices on a Si platform; and (ii) the co-integration of these device architectures with standard Si CMOS. In that context, it is critical to optimize the technology considering the material properties along with the electrical and thermal aspects.

In this PhD, you will contribute to solve this challenge by studying various substrate technologies from different perspectives:

  • Assess the effect on RF figures of merit (loss, crosstalk, distortion, ...) of the different interfaces created by advanced integration. These non-ideal interfaces are expected to present fixed charges and traps causing RF losses and non-linearities as well as frequency dependent phenomena;
  • Characterization of material properties of various substrates and thin films, for instance extraction of dielectric constant and losses from advanced on-wafer measurements in millimiter-wave domain, as well as analyze their thermal properties;
  • Simulation with TCAD tools and modelling the impact of substrates on the transistor and circuit performances;
  • Process optimization towards high performance and sustainable solutions.

Required background: Candidates are expected to have a Master’s degree in Electrical Engineering, Material science, Nanoscience and Nanotechnology or equivalent, with a solid background in semiconductor physics and excellent quantitative/analytical skills.

Type of work: Characterization: 50%, Modelling: 50%

Supervisor: Jean-Pierre Raskin

Co-supervisor: Bertrand Parvais

Daily advisor: Sachin Yadav

The reference code for this position is 2023-068. Mention this reference code on your application form.

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