Leuven | More than two weeks ago
For many years device, design, and system engineers have worked separately, assisted in their quest for increased performance by the "good scaling" of Moore's law. In recent years, due to new fundamental challenges, induced by both technological and physical limitations, traditional CMOS scaling has considerably slowed down.
This ever-increasing complexity of conventional technology scaling has led the industry to look more and more towards higher levels of abstraction to overcome scaling barriers. Co-Optimization between the software application and the SoC physical design is therefore very important to assess the impact that certain design choices, made during both stages, have on the rest of the abstraction chain. For example, depending on the level of parallelism in the software, adding more cores to the system can reduce latency, but it may lead to routing congestion in the physical design, jeopardizing the potential gains.
This project aims at achieving this co-optimization by building a link between these two aspects and identifying key design parameters (e.g. wirelength, switching information, etc...) to quantify their impact on performance, at different levels. To achieve this goal the student will need to create a feedback loop between a simulation framework (in-house or open-source resource) and the commercial EDA infrastructure available within imec. Activities will include simulating diverse application benchmarks for the evaluation of an existing architecture while at the same time feeding the results back to lower levels of abstraction, to optimize the physical design.
Type of project: Combination of internship and thesis, Thesis, Internship
Required degree: Master of Science, Master of Engineering Science
Required background: Computer Science, Electrotechnics/Electrical Engineering
Supervising scientist(s): For further information or for application, please contact: Giuliano Sisto (Giuliano.Sisto@imec.be)