System-level enablement of systolic architectures for AI applications

Despite the trend of moving the heavy computation of AI workloads to cloud servers, smaller workloads are executed in always-on edge devices, and this is particularly true for embedded AR/VR applications. One common and efficient way to execute such workloads is through using systolic array-based hardware accelerators to compute the matrix-matrix multiplications which are at the core of these workloads.

As part of this work, we aim to develop a programmable platform to control a systolic accelerator targeting AR/VR workloads which will help us to benchmark the full system PPA for different workloads and/or system constraints.

The student is expected to work with a RISC-V compiler toolchain and ISA as well as communication protocols between processor and accelerator. During the study, multiple dataflow strategies will be explored aiming to simplify the mapping of an AR/VR workload into the accelerator. The final aim of the work is to develop a programmable infrastructure where it is possible to control a systolic architecture that will execute an AI workload. In the process, the student is expected to closely work with engineers on exploring how to execute this integration and perform a PnR assessment of the full system.

Required background: Electrical engineering, RTL coding, basic understanding of ASIC flow, programming (C++/Python)

Type of work: 30% literature, 70% modelling

Daily advisor: Leandro M. Giacomini Rocha, Dwaipayan Biswas