PhD - Leuven | More than two weeks ago
To discover what “system-level ESD” means in the era beyond Moore’s transistor scaling - in the new device-technology co-optimization (DTCO) and system-technology co-optimization (STCO) scaling era.
With the use of 2.5D and 3D heterogeneous integration, the functions of the printed circuit boards are transferred into the chip itself. What was before “system-level ESD” at the board-level and above, now needs to step one level deeper to package-level. With multiple chips/chiplets and other components inside a single package, the definition of the system is changing.
If a chip package contains 50 components inside, do we call it a device or a system? What ESD robustness target should such a package have? Do we test for ESD robustness with system-level or device-level tests, or something in between? Apart from testing, how do we efficiently protect such a package from ESD? Do all 50 components need their own ESD protection circuits or is one enough to protect them all?
This PhD will try to answer all these questions. To do so, the candidate will become part of imec ESD team and therefore gain access to our lab and our knowledge on ESD measurements, data analysis, circuit design and modeling. Furthermore, they will work closely with the imec 3D integration program and learn about the latest trends in advanced chip/chiplet packaging.
The goal of this PhD is to discover what “system-level ESD” means in the era beyond Moore’s transistor scaling - in the new device-technology co-optimization (DTCO) and system-technology co-optimization (STCO) scaling era. More practically, this will involve:
It would be welcome, but we do not expect the candidate to have previous knowledge on ESD or advanced chip packaging technologies. What we do expect for the candidate to have:
In return, we will provide a daily supervisor experienced in guiding students to their goals. The ESD team is very supportive, international and ready to help when needed.
Required background: Master’s degree in Electronic Engineering or equivalent field; Preferred knowledge: VLSI Design, Layout/SPICE Design Environment, Circuit simulations, modeling and measurements, high-frequency measurements, PCB design.
Type of work: 10% literature, 10% advanced packaging and semiconductor technology study, 40% circuit design, modeling and layout, 25% experimental measurement and tester development, 15% circuit-system co-simulation and optimization (15%)
Supervisor: Dragomir Milojevic
Daily advisor: Marko Simicic and Nicolas Pantano
The reference code for this position is 2024-162. Mention this reference code on your application form.