Technology aware design optimization for PDK

As we continue to shrink our CMOS devices, the intricacy of our designs has grown significantly. This complexity, combined with the limitations of our manufacturing process, makes it harder to meet the speed and cost targets for our circuits. To overcome these challenges, it's crucial to thoroughly assess the design in relation to the specific technology, in order to maximize its advantages and gain a clear projection for future technological advancements.
 
 
While exploring new technology, benchmarking often concentrates mainly on the device itself, with limited attention given to design metrics like cell timing and power, and the potential for enhancing them is often overlooked. This exploration can have two major benefits: 1) Improving the quality of the PDK (Process Development Kit) providing suggestive feedback for the technology development 2) getting the best, accurate and robust output from the developed libraries for system level optimization. 
 
 
This project entails a targeted examination of commonly used standard cells found in critical circuit paths. The goal is to enhance their performance through a systematic design simulation and PDK (Process Design Kit) development framework, which will be applied for benchmarking at the library level.

Type of Project: Combination of internship and thesis 

Master's degree: Master of Engineering Science; Master of Science; Master of Engineering Technology 

Master program: Electrotechnics/Electrical Engineering; Nanoscience & Nanotechnology; Computer Science 

Duration: 4 - 6 Months 

For more information or application, please contact Arka Dutta (arka.dutta@imec.be)

Imec allowance will be provided.