The communication and compute component organisations in embedded systems
are a major source of cost and energy. The use of cheaper and very low leakage
thin film technology (TFT) materials to replace silicon CMOS potentially
allows to significantly improve on this. But we also want to exploit the
growing potential of 3D interconnect technologies. In this MSc thesis we
want to explore planar and 3D TFT-based combined circuit and architecture
solutions which reduce especially the overall system cost and system
energy consumption.
We will focus especially on computing components like
segmented bus and related communication blocks.
Simulations will be performed based on available measurement data to
calibrate the cost, energy and performance models.
Profile: Strong interest in circuit and architecture exploration and
simulation, basics of microelectronic technologies with emphasis on
thin film logic devices and 3D interconnect schemes
Type of project: Thesis
Duration: 6-9 months
Required degree: Master of Engineering Technology, Master of Engineering Science
Required background: Electrotechnics/Electrical Engineering
Supervising scientist(s): For further information or for application, please contact: Kris Myny (Kris.Myny@imec.be) and Francky Catthoor (Francky.Catthoor@imec.be)