Time-Dependent Dielectric Breakdown of Replacement Metal Gate stacks for Advanced Logic Devices beyond the 2nm CMOS node

To support the unabated performance enhancement of CMOS technology, which fuels innovation of all fields of our society, the MOSFET device architecture has reached extraordinary degrees of scaling and complexity. A decade ago industry moved from the classic planar transistor to finFET architectures, and it currently prepares to switch to the even more complex NanoSheet structure. Beyond that, novel concepts minimizing the footprint of a single logic gate (an nMOS and a pMOS transistor combined) are currently being explored, including the ForkSheets (lateral co-integration) and the CFETs (vertical stacking). Each subsequent device technology must offer enhanced performance while guaranteeing sufficient reliability.

Time-Dependent Dielectric Breakdown (TDDB) is one of the fundamental MOS transistor failure mechanisms. During continuous device operation defects are generated across the gate dielectric due to the application of a gate bias, eventually resulting in a loss of the dielectric’s insulating properties. TDDB has been extensively studied in the early decades of CMOS technology, when relatively high operating voltages (5/3.3/2.5/1.8V) were standard. In recent years, with the aggressive scaling of transistor gate length and dielectric thickness, the CMOS operating voltage has dropped below 1V: as a consequence, the primary focus of reliability research has shifted for a while towards other aging mechanisms, such as Bias Temperature Instability, which induce a gradual drift of the device properties instead of a sudden failure.

Meanwhile the gate dielectric technology has been advanced substantially, requiring a thorough reassessment of TDDB reliability and its physics-based models. After the introduction of high-k dielectrics, which replaced the native Si oxide ~15 years ago, the gate stack fabrication flow has moved from the traditional “Gate-First” integration to the so-called “Gate-Last” or “Replacement Gate” integration, where a dummy gate stack used for the self-aligned source/drain fabrication is replaced by the final high-k dielectric only towards the end of the fabrication flow. In this scheme, the gate dielectric is not exposed to the high temperature anneals required for channel doping activation—this approach thus enables the usage of different metals (even some with limited thermal stability) as gate electrodes to control the transistor threshold voltage (V_th) but requires dedicated anneals to cure dielectric defects after deposition.

In current technology nodes, the offering of multiple transistor flavors with different V_th’s obtained with different gate metal stacks has become standard as it allows for larger flexibility in the design of Systems on Chip (SoC), using, e.g., low V_th transistors for high performance circuits and high V_th transistors when low power consumption is the priority. Furthermore, a variety of treatments has been developed to cure dielectric defects, including post-deposition and post-metal anneals; in particular, with transistor stacking envisioned as the primary path towards further CMOS technology scaling, efforts are currently focused on the development of low thermal budget, plasma-based treatments for dielectric quality improvement in NanoSheets and CFETs. The plethora of novel gate stacks currently available (various metal stacks, various treatments, different channel polarity, various device architectures) calls for a fundamental reassessment of TDDB.

This PhD study will focus on:

1. Experimental characterization of TDDB in advanced gate stacks for both nMOS and pMOS devices, with different gate metals and dielectric treatments;
2. Development of novel physics-based gate stack reliability benchmarking strategies. E.g., simple voltage-driven device lifetime models are not suitable for comparing multi-Vth stacks for which a given operating voltage results in vastly different electric fields and gate leakage, and thus different defect generation rates. Proper, physics-based benchmarking is crucial also to identify extrinsic cases (e.g., anomalous defectivity due to metal/dielectric intermixing);
3. Expanding existing degradation models (single dielectric layer, voltage driven) towards carrier energy-driven degradation models generally applicable to any MOS system.

The PhD candidate will be embedded in the Device Reliability and Electrical (DRE) characterization team of imec, which has a strong expertise in reliability characterization and modeling and established characterization labs to support this study.