Unconventional SRAMs for future AI & ML applications

It has been estimated that over the period when Moores Law scaling delivered 8x AI training speedup, 25x came from algorithmic efficiency and 37,500x came from scale up – more GPUs and more datacenters. But while AI/ML workloads and chip volumes are exploding, logic density scaling has slowed and SRAM density scaling has stalled. Further, performance and stability of SRAM are greatly compromised due to process induced variability in advanced technology nodes. Next generation AI/ML applications demand ever more scale, and in the absence of underlying SRAM scaling, this will lead to rising dollar and environmental costs.

Emerging devices such as fork-sheet, complementary FET, magnetic devices have been perceived as promising candidates for SRAM bitcell scaling in advanced technology nodes. Furthermore, various 3D integration technology options such as face-to-face, face-to-back, and sequential 3D CMOS technologies such as Array-under-CMOS (AuC) are emerging to increase system-on-chip (SoC) level SRAM density beyond traditional CMOS technology scaling. In parallel there is a research trend towards SRAM circuits that are optimized specifically for AI and ML applications, rather than general purpose compute usage.

In this work the candidate will interact with different imec groups working on technology development, TCAD simulation, circuits and system design to identify the challenges and opportunities of SRAM design. The primary objectives of this PhD include understanding memory demand and trade-offs of AI/ML applications, developing SRAM architecture to deliver workload performance, efficiency, and cost benefits. This includes workload specific explorations such as exploitation of sparsity, sequential access, compute in periphery, transpose read/write and other cross stack approaches. The ideas developed in the work will contribute to and benefit from the imec System-Technology Co-Optimization (STCO) program.