Understanding the coupling between localized heating and electromigration failures in the BEOL

Leuven - PhD
More than two weeks ago

Will FinFET self-heating hamper electromigration reliability in future technology nodes?


For several decades, on-chip interconnections in the back end of the line (BEOL) have been integrated using low-resistive Cu. However, scaling of the BEOL dimensions has not only degraded the intrinsic properties of the Cu (such as increased resistivity ρ), but also the electromigration (EM) reliability has been impacted. The EM is understood as atomic diffusion under influence of an electric wind. Moreover, due to scaling, the interconnect cross sectional area ratio of the interconnect liner (to prevent Cu diffusion) with respect to actual Cu filling is increasing​. The above described effects in ρ and EM reliability were caused primarily by increasing their contributions from electron scattering with interfaces and grain boundaries, and increased EM-induced mass flow. These effects are aggravated by the increased drive current densities of FinFETs and their local self-heating effects. To improve EM reliability, Cu is being replaced by alternative metals which exhibit higher electrical resistivity and lower thermal conductivity. Although simple models (e.g. Black's equation) exist to predict the EM lifetime under increased temperatures, little is known about the effects of localized thermal hotspots and thermo-mechanical cycling in these wires.

During this PhD, you will design and develop test-structures to assess the temperature gradients in the BEOL under the influence of device level self-heating, study the electromigration properties and leverage the understanding of temperature effects in the existing EM models. Your daily activities will involve designing of test-structures in imec's state-of-the-art technologies, as well as in mature commercial technologies. You will get the chance to characterize your own designs and to develop models in this little-explored territory of semiconductor reliability.


During this PhD you will get the opportunity to develop a wide set of skills, ranging from test structure design and layout, up to electrical and physical characterization and model development. You will get a chance to learn from and work with experienced researchers and designers at IMEC in many domains of semiconductor technologies.


Our expectations: a thorough semiconductor device physics background, willingness to pick up diverse skills (e.g. design and layout in advanced CMOS technologies), hardworking, curious in nature and with an analytical mind. Experience in electrical characterization and/or integrated circuit design is a plus.​




Required background: Engineering Technology, Electrical Engineering, Nanoscience, Physics


Type of work: 10% literature study, 40% experimental and characterization work, 25% modeling and simulation, 25% design

Supervisor: Guido Groeseneken

Daily advisor: Erik Bury

The reference code for this position is 1812-40. Mention this reference code on your application form.


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