Universal SRAM Memory Compiler Development: Empowering Technology Node Compatibility
Master projects/internships - Leuven | More than two weeks ago
The overarching goal of this project is to construct and code a model memory compiler that enables us to generate compilers for advanced nodes.
Transitioning from one technology node to the next presents increasing challenges. This growing complexity doesn't solely arise from transistor miniaturization but also encompasses the intricacies of the backend of line (BEOL), which acts as the nanoscale interconnect. Consequently, the design of SRAM memories becomes a more intricate task. SRAM is frequently employed in processor caches due to its ability to swiftly access frequently used data, ultimately enhancing overall system performance.
To streamline the SRAM circuit design process, automation is essential. This automation involves coding with two primary objectives: firstly, combining various types of leaf cells into tiles to meet memory size requirements, and secondly, ensuring that the coding is generic enough to function across various technology nodes.
Electronic design automation (EDA) tools can simulate and characterize the performance impact of different memory sizes. However, manually conducting these tasks for diverse memories across multiple nodes and technologies is time-consuming and resource intensive. To expedite this phase, we've developed a model memory and are now working on creating a versatile code for its tiling.
The overarching goal of this project is to construct a model memory compiler that enables us to generate compilers for advanced nodes.
Therefore, the initial step necessitates a solid grasp of layout design, SRAM memory fundamentals, and a deep understanding of coding. This knowledge is subsequently applied to arrange the available leaf cells into tiles tailored to the desired memory size, such as 128x128 or 40x10 (word lines x bit lines).
Type of Project: Combination of internship and thesis; Internship
Master's degree: Master of Science; Master of Engineering Technology
Master program: Electrotechnics/Electrical Engineering
Duration: 3 - 4 months
For more information or application, please contact Priyanka Pandey (priyanka.pandey@imec.be)