PhD - Leuven | Just now
Magnetic random access memory (MRAM) has made extensive progresses to be a working memory solution with nonvolatility, high speed and low power consumption, exploiting spin-transfer torque (STT) as the key ingredient for fully electric operation. However, STT writing requires a substantial amount of spin-polarized currents flowing through the oxide barrier of a magnetic tunnel junction (MTJ), which ends up in a clear limit for reducing further the power consumption. Such intense tunneling current can also degrade the barrier of MTJ to affect the reliability of memory cells. In addition, it is difficult for the speed of STT writing to reach GHz regime, regarding the general dynamics of magnetization in ferromagnetic layer.
Voltage-controlled magnetic anisotropy (VCMA) is highlighted as a next generation write scheme for MRAM to enable GHz-speed and ultra-low power operations , along with spin-orbit torque (SOT) using spin Hall effect (SHE), where in-plane charge current flowing in a nonmagnetic layer generates a vertical spin current, leading to the magnetization reversal of the adjacent magnetic layer . VCMA reduces the interfacial perpendicular magnetic anisotropy (PMA) with an electric field, or a voltage across the barrier in MTJ. Hence, switching of magnetization by eliminating the PMA using voltage pulse without current is the key aspect of VCMA. Understanding on the fundamental characteristics in VCMA-induced switching of MTJ made good progress in IMEC . Moreover, IMEC demonstrated solutions to overcome important challenges such as implementation of in-plane magnetic field generator and deterministic VCMA switching scheme .
Intensive efforts have been made to understand the fundamental aspects of VCMA operation. However, a lot more of understanding and improvement are required for VCMA to become a real solution for application. First, the VCMA coefficient, representing the efficiency of changing anisotropy with given voltage, should be improved significantly, to switch a MTJ device with sufficiently high anisotropy and long data retention time . Materials investigation to tune the interface is the fundamental aspect, and exploration of alternative structure of the free layer such as synthetic antiferromagnetic structure can be another aspect to improve the switching efficiency by VCMA effect. Plus, write pulse width for VCMA switching has to be very precisely defined allowing the variation less than a few hundred picoseconds. The pulse width window for reliable switching has to be widened in application point of view. It is also related to the behavior of write error rate (WER) and its improvement. Writing voltage has to be evaluated also considering the range of breakdown voltages. High-WER range is also important since 1 – WER is another crucial parameter read disturbance rate (RDR). VCMA-MRAM device needs to allow a certain amount of current to flow for reading in general. Characteristics in the range of reading is equally important to realize VCMA-MRAM.
Overall, the scope of the present topic is to study the VCMA writing characteristics from various materials and different stack configurations, correlating write performance with other parameters of MTJ including VCMA coefficient. Write performance can extend to WER estimation which will make the margin between the voltage for reliable switching and the breakdown voltages. Achievements can extend to propose a breakthrough in writing scheme to switch high retention device with low write voltage and energy. Device design to improve the read characteristic can also be additional achievement.
Practically, you will be embedded inside the (magnetic) device characterization team. You will study the switching performance of different material stack. It is expected that your feedback will help guide future development of the material. It is also expected that your in-depth study will help unravel (and possibly resolve) the major challenges remaining on the path of the ultra-low power VCMA device. Alongside the experimental work, micromagnetic simulation can be part of this PhD topic, to elucidate and guide the device operation and failure modes.
 T. Maruyama et al., Nat. Nanotechnol. 4, 158 (2009)
 I. M. Miron et al., Nature 476, 189 (2011)
 Y. C. Wu et al., AIP Advances 10, 035123 (2020)
 Y. C. Wu et al., IEEE Symp. VLSI Tech., TMFS.4 (2020)
 T. Nozaki et al., Micromachines 10, 327 (2019)
Required background: solid state physics, material science, electrical engineering, fundamentals in spintronics
Type of work: 40% device electrical testing, 30% data analysis, 20% device modeling and design, 10% literature
Supervisor: Kristiaan Temst
Co-supervisor: Jan Van Houdt
Daily advisor: Woojin Kim
The reference code for this position is 2021-019. Mention this reference code on your application form.