Wafer scale aligned semiconducting carbon nanotubes (CNTs) for future CMOS logic

Abstract:

Aligned carbon nanotubes are a promising material candidate for next-generation field-effect transistors (FETs) due to their unique intrinsic properties (e.g. ballistic transport, excellent charge carrier mobility and high thermal conductivity). The ideal CNT material system for high-performance transistors consists of well-aligned CNTs with a consistent pitch (~100-200 CNTs/µm), a semiconducting purity estimated to be >99.9999% and a narrow CNT diameter distribution [1,2]. Significant progress in CNT purification, assembly from solution into densely aligned arrays and subsequent integration in devices was recently shown [3-5]. This demonstrates that the CNT material remains not only scientifically attractive but offers a technologically feasible pathway towards high-performing and ultimately scaled FETs.

In this PhD work you will contribute to the development of a CNT-based platform to enable smaller footprint and better device performance with the focus on material development and characterization. You will develop competences and expertise in various techniques to characterize aligned CNT arrays, including the degree of alignment, density, purity, uniformity, CNT diameter, defects etc. The lack of reliable and high-throughput techniques to quantitatively assess the purity of CNTs for material refinement and quality control remains a challenge for the future CNT device manufacturing [2]. Approaches for material characterization, visualization and quantification over wafer scale prior to device fabrication should be developed. Exploration of benign solutions for cleaning the CNT arrays from the polymer residue remaining from the CNT alignment and device fabrication might be required to improve device performance and reliability. In collaboration with the project partners from top research groups both internationally and inside imec, you will work towards true understanding of the aligned CNT material properties, quality optimization and integration to assess the CNT-based device performance. Part of the challenges will eventually be establishing guidelines for fab-compatibility of aligned CNT wafers in advanced nodes based on IMEC's infrastructure.  Your PhD work will bring aligned CNT-based scaled logic transistors closer to the industry to help sustain Moore’s law beyond the physical limits of silicon.

Profile

Are you interested in working as part of the team that explores next generation materials for high-performance electronics? As the topic starts with characterizing aligned CNTs, a broad interest in different characterization methods (Raman, photoluminescence, scanning electron microscopy (SEM), surface probe microscopy (SPM), atomic force microscopy (AFM) techniques and electrical transport measurements) is preferred. A genuine interest in semiconductor physics and surface chemistry is desired. Experience with polymer chemistry and/or self-assembly is considered a plus as this understanding can be beneficial to further optimize and scale up the CNT alignment approaches . You are a curious, independent, and resourceful person. The ability to communicate fluently in English is an absolute requirement in IMEC’s international environment.

[1] Liu et al, Science 368, p. 850 (2020)

[2] Cao, Nano Research, 14 (9) (2021)

[3] Lin et al, Adv. Func. Mat., 2104539 (2021)

[4] Jinkins et al, Sci. Adv. 7 (2021)

[5] Bishop et al, Nature Electronics, 3 (2020)