High-speed analog/RF

Leveraging imec’s broad expertise in a variety of technologies, we develop RF front-end technologies for mobile handsets that meet the requirements of 5G. Together with our program partners, we explore hybrid III-V/Si technology to take RF beyond the speed and power limits of CMOS technologies.

Introduction

The advent of 5G will not only bring great new opportunities but also new challenges for the technologies enabling this next-generation of mobile communications. Not only innovations in the overall network infrastructure will be needed, but also in the technologies for the mobile devices themselves.

With a proven track record in III/V-on-300mm Si and GaN-on-200mm Si technologies, in sub-6GHz and mm-wave wireless communication, in CMOS technologies, and in modelling and circuit design technologies, imec is uniquely placed to develop RF front-end technologies for 5G mobile handsets.

About the program

Together with materials and equipment suppliers, IDM’s, foundries and system companies, we jointly explore hybrid Si/III-V technologies to enable highly performant RF front-end devices for 5G. The devices will operate at both the sub-6GHz bands and mm-wave bands. We target the development of high-speed devices with a strong driving capability to generate a high output power at a high power efficiency.

Our focus is on the following architectures:

  • IIIV high electron mobility transistors (HEMTs), both GaAs and InP based, and III-N HEMTs
  • IIIV and III-N MOSFET devices
  • IIIV heterojunction bipolar transistors (HBT)

The program runs in two phases:

Integration of standalone non-Si RF devices on a 200mm and 300mm platform

We target the development of specific process steps and modules that are critical for integrating III-V and III-N standalone devices on a 200mm and 300mm Si platform:

  • Modules targeting the reduction of parasitics in nonSi devices
  • Epitaxial growth of IIIV and III-N buffer layers
  • Modules for gate stack assessment and optimization
  • CMOS compatible backend-of-line processes
  • ...

Co-integration with Si CMOS

In a second phase, III-V/III-N devices are co-integrated with standard Si CMOS. The goal is twofold:

  • Enabling a higher degree of integration for all building blocks of the RF frontend module
  • Improving the energy efficiency of the overall circuit.

We explore several approaches for the co-integration:

  • Monolithic or 2D integration
  • 3D integration (3D stacking and sequential3D)

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