The semiconductor industry has been able to reduce the cost per function and increase the function density steadily over the last three decades. At the same time, the different abstraction levels separating semiconductor design and manufacturing have enabled efficient product design cycles and fast time-to-market. However, economical and technical issues may slow down the scaling effort. To keep on reducing the cost per function, one possibility is to move to a 3-Dimensional stacking of ICs (3D-IC). Using 3D chip stacking, it is possible to extend the number of functions per 3D chip well beyond the near-term capabilities of traditional scaling.
To reduce area, increase device density and extend performance and/or IC functionality, imec’s R&D on 3D-IC technology explores cost-effective realization of 3D interconnect technology with through-silicon-via (TSV).
Imec also explores 3D design to propose methodologies for critical design issues, enabling effective use of 3D interconnection on system level.
- Electrical, thermal and thermo-mechanical characterization and optimization
- Chip-package interaction
- Cost modeling
- 3D design and test