Semiconductor technology & processing

15 min

Een nieuwe chip-verpakkingstechniek voor mobiele toepassingen

Imecs nieuwe ‘fan-out wafer-level packaging’-techniek creëert een grote dichtheid aan verbindingen tussen de chips onderling, en is een interessante optie om chips in bijv. smartphones te verpakken.

Dit artikel is enkel beschikbaar in het Engels.

Imec presents a novel approach to fan-out wafer-level packaging that answers the need for higher-density, higher-bandwidth chip-to-chip connections. Arnita Podpod, senior R&D engineer at imec, and Eric Beyne, imec fellow and program director of imec’s 3D system integration program, introduce the technology, discuss the main challenges and assets, and list the potential applications.

Wafer-level packaging: an attractive packaging solution for mobile applications

Today, many electronic systems still consist of a multitude of components that are packaged individually after wafer dicing, and are interconnected using conventional printed circuit boards. However, for more ‘demanding’ applications, advanced 3D integration and interconnect technologies have emerged through the years – which have largely reduced the size of the electronic systems, and have enabled faster and shorter connections between their sub-circuits. One of these technologies is wafer-level packaging (WLP), where multiple dies are packaged while they are still on the wafer. Since the entire wafer is now packaged at once, this solution is more cost-effective than the traditional packaging approaches. In addition, the resulting packaged chips are smaller and thinner in size, which is an important consideration in footprint-sensitive devices such as smartphones. In today’s smartphones, on average five to seven wafer-level packages can already be found, and the numbers continue to increase. 

Fan-in and fan-out

There are two main types of wafer-level packages: fan-in and fan-out. They differ in the way the redistribution layer is incorporated in the package. Redistribution layers, usually organic layers, are used to re-route the dies connections (I/Os) to the desired (bump) location on top of the die surface. With fan-in, the redistribution layer traces are routed inwards, creating a very small package (roughly corresponding to the size of the die itself). But the redistribution process can also be used to expand the available area of the package, by spreading or ‘fanning out’ the contacts beyond the dimensions of the chip. In general, this fan-out WLP (FO-WLP) technology provides a larger I/O count than fan-in WLP technology.

In mobile applications, fan-out wafer-level packages are gradually replacing the more traditional package-on-package (PoP) memory-on-logic solutions.

These PoPs are much thicker than fan-out concepts and suffer from limited interconnect bandwidth and density, and from limited pitch scaling (a few 100µm). In these applications, FO-WLP is preferred over other available high-bandwidth 3D technologies as well, such as 3D stacking (in which hot spots in the logic die may affect the memory retention) or 2.5 stacking (where the longer interconnects generate a higher interconnect power and additional cost).

Two basic ‘fan-out’ process flows

Various FO-WLP approaches have been developed and established over the past years to answer the increasing need for high data rates and wide I/O count, and to answer the demand for increased function integration on the package. All these approaches start from  one of the two basic fan-out process flows: the ‘mold first’ or the ‘redistribution layer first’ flow. 

Following the mold first approach, dies are first assembled on a temporary carrier, followed by wafer over-molding. The function of the epoxy molds is to protect the individual components and hold them all together. In a final stage, the redistribution layer is created and connections are made. Following the redistribution layer first approach, die assembly and wafer over-molding is performed after the creation of the redistribution layer. 

Each of these approaches comes with its own set of drawbacks. In the mold first approach, for example, the dies usually shift during or after over-molding, and this makes it very challenging to achieve interconnect pitches below 100µm. With the redistribution layer first approach, the achievable density is limited by the line and space resolution enabled by the (organic) redistribution layer. 

Flip-chip on FO-WLP: a new ‘fan-out’ approach for higher interconnect densities 

To answer the need for higher-density, higher-bandwidth chip-to-chip connections, the imec team has developed a novel FO-WLP approach on 300mm wafers, referred to as flip-chip on FO-WLP. 

This new concept basically uses a mold first approach, but the dies are now over-molded after the formation of the chip-to-chip interconnections. This way, contrary to the standard mold first approach, chips are already interconnected before being shifted during the over-molding process.

The advantages of this approach (e.g. lower die shift) will be explained below, along with the challenges. 

Key components: through-package vias (TPV) and Si bridges

In this work, a test vehicle has been used to demonstrate the feasibility of the new fan-out concept. The test vehicle is composed of seven individual chip components: wide I/O DRAM, Flash memory, logic, two through-package vias and two Si bridges. The test vehicle is used to obtain practical learnings. Therefore, the logic and memory dies are not fully functional: they are ‘mimic’ dies, used to test the electrical continuity between the bump connections.

The interconnecting Si bridges and the through-package via chips are key components to realize the high-density connections. Through-package via chips are Si dies with through-Si vias (TSVs) and bumps of 40µm pitch. The Si bridges have bumps of 40µm and 20µm pitch. These components form a bridge between the functional dies (e.g. the logic and memory dies), enabling ultrahigh chip-to-chip interconnect densities with 20µm bump pitch.

Another key differentiator with respect to standard mold first approaches, is the tight alignment step. During this critical assembly step, the individual dies are placed with high precision on a flat temporary bonding Si wafer.  

Concept of the flip-chip on fan-out wafer-level package.Concept of the flip-chip on fan-out wafer-level package.

A closer look at the process flow

In a first step of the assembly process flow, the through-package via and logic dies are placed on a carrier wafer with a temporary bonding layer on top. Next, the Si bridge (with 40µm and 20µm bump pitches) is attached using a thermocompression bonding (TCB) step. In this process step, bumps with 40µm pitch are attached to the through-package via side and to the left side of the logic die. The 20µm pitch bumps are attached to the right side of the logic die. In a next step, the wafer is over-molded by a liquid mold compound. Tests revealed a complete filling, even of the area under the bridge. Afterwards, the Cu pillars are exposed through grinding – to connect with the redistribution layer later on. After flipping the thinned wafer to a second carrier and removal of the first carrier, the memory dies are assembled using flip-chip technology. A second wafer-level molding and removal of the second carrier complete the process flow. In between process steps, continuity tests are performed to verify the electrical paths. The result is a complete package of only 300-400µm thickness (excluding the solder balls).

Flip-chip on FO-WLP: assembly process flow.

Flip-chip on FO-WLP: assembly process flow.

Pictures illustrating steps 5 to 8. (Left) after die placement and bridge bonding; (middle) after molding and back-grinding and (right) exposed Cu pillars on package surface.Pictures illustrating steps 5 to 8. (Left) after die placement and bridge bonding; (middle) after molding and back-grinding and (right) exposed Cu pillars on package surface.

Cross-section after flip-chip on FO-WLP package assembly and final, second wafer-level molding.

Cross-section after flip-chip on FO-WLP package assembly and final, second wafer-level molding.

Major challenges and solutions

The process flow came with its own set of challenges that needed to be overcome to ensure fully functional package solutions with ultrahigh chip-to-chip interconnect density.

One of the concerns was the possible tilting of the dies during the assembly process flow, especially for the long and narrow through-Si vias and Si bridges. Tilting of these dies might break the interconnections between the sub-components. To assess whether and when tilting takes place, the imec team applied different forces for placing the through-package vias. The team observed that, even for the largest placement force, tilting was limited to below 5µm – sufficiently low to maintain the connections.

Next, the alignment between the logic and through-package dies has received considerable attention, and can be considered a key differentiator of the FO-WLP approach.

The logic and through-package dies should be placed very close to each other, and a precise alignment step is needed to enable the subsequent 40µm and 20µm bump pitch stacking of the Si bridge. For example, to achieve the required 20µm bump pitch, a misalignment of max +/-3µm between the logic and through-package die can be tolerated. To reach this exceptionally small misalignment, the team incorporated alignment marks into the carrier and die designs. Logic dies were first aligned to the carrier. Next, through-package dies were placed, aligned to the carrier and to the logic dies. Finally, a high accuracy placement and stacking thermocompression bonding tool was used to attach the Si bridge. 

Illustration of the successful bridge-to-logic bonding at 40µm pitch, compatible with 20µm pitch microbump assembly.

Illustration of the successful bridge-to-logic bonding at 40µm pitch, compatible with 20µm pitch microbump assembly.

During the subsequent molding process, the dies can still shift – thereby damaging or breaking the bump connections between through-package via and bridge, or between logic and bridge. The imec team therefore performed dedicated electrical tests, before and after the molding. The tests revealed that the molding process did not affect the integrity of the connections. Based on these results, it can be assumed that, if the dies shift upon molding, they do this in the same direction, as a whole, without breaking the connections.

 Summary and future outlook

With this novel approach, the imec team demonstrated a record high chip-to-chip interconnect density with 20µm bump pitch in a fan-out context. In the near future, the technology will be further improved, and the electrical and RF behavior will be evaluated in different configurations. 

The presented technology is especially attractive for mobile applications, as it enables a cost-effective wide I/O memory-to-logic interconnect in a very small form factor.

Ultimately, flip-chip on FO-WLP may also become an enabling technology for heterogeneous integration, targeting high-performance applications. It can provide a way to incorporate multiple dies – including high-performant compute, memory and optical communication blocks – in an electrical highly interconnected package. 

 This article was first published in Chip Scale Review (March – April 2019). 

 

Want to know more?

  • Imec presented more details on the above technology in the 2018 IWLPC paper ‘High density and high bandwidth chip-to-chip connections with 20µm pitch flip-chip on fan-out wafer level package’ by A. Podpod et al. For this paper, A. Podpod received the 2018 IWLPC Best Paper Award. If you would like to receive a copy of this paper, you can request one via our contact form.
  • You can find a broader vision on 3D technology in imec magazine.

About Arnita Podpod

Arnita Podpod graduated with a master degree in Materials Science and Engineering, and with a bachelor degree in Applied Physics from University of the Philippines. After graduation, she started at NXP Semiconductors as a Project (Materials) and Process Engineer, and progressed to being a Senior Package Development Engineer with Fairchild Semiconductor Phils. Arnita joined imec in 2013 as a Senior R&D Engineer and is currently responsible for both Flip Chip on FO-WLP projects and Pre-Assembly module integration within the imec 3D program.

About Eric Beyne

Eric Beyne obtained a degree in electrical engineering in 1983 and the Ph.D. in Applied Sciences in 1990, both from the Katholieke Universiteit Leuven, Belgium. Since 1986 he has been with imec in Leuven, Belgium where he has worked on advanced packaging and interconnect technologies. Currently, he is imec fellow and program director of imec’s 3D System Integration program. He received the European Semi Award 2016 for contributions to the development of 3D technologies.

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